Semiconductor device

1 . A semiconductor device, comprising:

a substrate including active regions extending in a first direction;

a device isolation layer surrounding the active regions on the substrate;

gate structures intersecting the active regions and extending on the substrate in a second direction;

source/drain regions on the active regions at sides of the gate structures;

contact plugs on the source/drain regions and connected to the source/drain regions, respectively;

a vertical buried structure penetrating through at least a portion of the device isolation layer, spaced apart from the gate structures in the second direction, and in contact with at least one of the contact plugs;

a vertical insulating layer covering at least a portion of side surfaces of the vertical buried structure;

a horizontal buried structure below the vertical buried structure;

a first conductive barrier covering at least a portion of an upper surface and side surfaces of the horizontal buried structure; and

a metal-semiconductor compound pattern between the vertical buried structure and the first conductive barrier,

wherein the vertical buried structure is between source/drain regions adjacent to each other in the second direction among the source/drain regions at the sides of the gate structures.

2 . The semiconductor device of claim 1 , wherein an upper surface of the vertical buried structure is on a level higher than a level of an upper surface of each of the source/drain regions.

3 . The semiconductor device of claim 1 , wherein a lower surface of the vertical buried structure is on a level lower than a level of a lower surface of each of the source/drain regions.

4 . The semiconductor device of claim 1 , further comprising:

a plurality of channel layers spaced apart from each other in a third direction perpendicular to an upper surface of the substrate and surrounded by the gate structures on each of the active regions,

wherein an upper surface of the vertical buried structure is in contact with a lower surface of the contact plugs.

5 . The semiconductor device of claim 1 , wherein, in the vertical buried structure, both side surfaces in the second direction include regions having different slopes.

6 . The semiconductor device of claim 1 , wherein the metal-semiconductor compound pattern is spaced apart from the substrate by the vertical insulating layer.

7 . The semiconductor device of claim 1 , further comprising:

a first interlayer insulating layer covering at least a portion of the source/drain regions, the gate structures, and the device isolation layer.

8 . The semiconductor device of claim 1 , wherein the vertical insulating layer is in contact with the first conductive barrier.

9 . The semiconductor device of claim 1 , wherein the metal-semiconductor compound pattern is in contact with the vertical buried structure, the vertical insulating layer, and the first conductive barrier.

10 . The semiconductor device of claim 1 , wherein the metal-semiconductor compound pattern penetrates at least a portion of the substrate.

11 . The semiconductor device of claim 1 , wherein the vertical insulating layer covers at least a portion of a side surface of the metal-semiconductor compound pattern.

12 . The semiconductor device of claim 1 , further comprising:

a second interlayer insulating layer covering at least a portion of the horizontal buried structure and the metal-semiconductor compound pattern.

13 . The semiconductor device of claim 12 , wherein an uppermost portion of the second interlayer insulating layer is on a level higher than a level of a lowermost portion of the device isolation layer.

14 . A semiconductor device, comprising:

a substrate including active regions extending in a first direction;

a device isolation layer surrounding the active regions on the substrate;

gate structures intersecting the active regions and extending on the substrate in a second direction;

source/drain regions on the active regions at sides of the gate structures;

contact plugs on the source/drain regions and connected to the source/drain regions, respectively;

vertical buried structures including a first vertical buried structure penetrating through at least a portion of the device isolation layer, and a second vertical buried structure spaced apart from the gate structures in the second direction and in contact with at least one of the contact plugs;

a vertical insulating layer covering at least a portion of side surfaces of the vertical buried structures;

a horizontal buried structure on a lower surface of the first vertical buried structure; and

a first conductive barrier covering at least a portion of an upper surface and side surfaces of the horizontal buried structure,

wherein the vertical buried structures are between source/drain regions adjacent to each other in the second direction among the source/drain regions at the sides of the gate structures.

15 . The semiconductor device of claim 14 , wherein the first vertical buried structure and the second vertical buried structure include substantially the same material.

16 . The semiconductor device of claim 14 , further comprising:

a metal-semiconductor compound pattern between the first vertical buried structure and the first conductive barrier.

17 . The semiconductor device of claim 14 , further comprising:

a second conductive barrier between the first vertical buried structure and the first conductive barrier.

18 . The semiconductor device of claim 17 ,

wherein a lowermost portion of the first vertical buried structure is disposed in the device isolation layer, and

wherein the second conductive barrier is in contact with the first vertical buried structure and the first conductive barrier.

19 . The semiconductor device of claim 17 , wherein the second conductive barrier includes at least one of Ti, TiN, Mo, MoN, Ta, and TaN.

20 . A semiconductor device, comprising:

a substrate including active regions extending in a first direction;

a device isolation layer surrounding the active regions on the substrate;

gate structures intersecting the active regions and extending on the substrate in a second direction;

source/drain regions on the active regions at sides of the gate structures;

contact plugs on the source/drain regions and connected to the source/drain regions, respectively;

vertical buried structures including a first vertical buried structure penetrating through at least a portion of the device isolation layer and a second vertical buried structure on the first vertical buried structure and in contact with at least one of the contact plugs;

a vertical insulating layer covering at least a portion of side surfaces of the vertical buried structures;

a horizontal buried structure below the first vertical buried structure; and

a metal-semiconductor compound pattern on the first vertical buried structure and the horizontal buried structure,

wherein an upper surface of the second vertical buried structure is on a level higher than a level of an upper surface of each of the source/drain regions, and

wherein a lowermost portion of the vertical insulating layer is on a level lower than a level on which a maximum width of each of the source/drain regions in the second direction is disposed.