Selectively thinned gate-all-around (GAA) structures
Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.
1 . An integrated circuit comprising:
a first semiconductor device having a first semiconductor nanoribbon or nanowire extending between a first source region and a first drain region, the first semiconductor nanoribbon or nanowire having a first length and a first width, and a first subfin beneath the first semiconductor nanoribbon or nanowire and having the first width; and
a second semiconductor device having a second semiconductor nanoribbon or nanowire extending between a second source region and a second drain region, the second semiconductor nanoribbon or nanowire having a second length and a second width, the second width less than the first width, and a second subfin beneath the second semiconductor nanoribbon or nanowire and having the first width;
wherein semiconductor nanoribbon or nanowire length corresponds to a first distance between the corresponding source and drain regions, and semiconductor nanoribbon or nanowire width corresponds to a second distance between sidewalls of the corresponding nanoribbon or nanowire, the second distance extending in a horizontal direction that is orthogonal to a horizontal direction in which the first distance extends.
2 . The integrated circuit of claim 1 , wherein the first and second subfins each includes a tapered profile, and wherein sidewalls of the first subfin are collinear with the sidewalls of the first semiconductor nanoribbon or nanowire, and sidewalls of the second subfin are not collinear with the sidewalls of the second semiconductor nanoribbon or nanowire.
3 . The integrated circuit of claim 1 , wherein the first semiconductor device is an n-channel device and the second semiconductor device is a p-channel device.
4 . The integrated circuit of claim 1 , wherein the second width is at least 50% less than the first width.
5 . The integrated circuit of claim 1 , wherein an imaginary horizontal plane at least partially passes through each of the first and second semiconductor nanoribbons or nanowires.
6 . A die comprising the integrated circuit of claim 1 .
7 . An electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor device having a first body of semiconductor material extending between a first source region and a first drain region and having a first subfin beneath the first body of semiconductor material, the first body of semiconductor material having a first width that is substantially the same as a width of the first subfin; and
a second semiconductor device having a second body of semiconductor material extending between a second source region and a second drain region and having a second subfin beneath the second body of semiconductor material, the second body of semiconductor material having a second width that is less than a width of the second subfin and less than the first width;
wherein the first body of semiconductor material is a first semiconductor nanoribbon or nanowire, and the second body of semiconductor material is a second semiconductor nanoribbon or nanowire.
8 . The electronic device of claim 7 , wherein both the first subfin and the second subfin have substantially the same width.
9 . The electronic device of claim 7 , wherein the first and second subfins each includes a tapered profile, and wherein sidewalls of the first subfin are collinear with the sidewalls of the first body of semiconductor material, and sidewalls of the second subfin are not collinear with the sidewalls of the second body of semiconductor material.
10 . The electronic device of claim 7 , wherein the first semiconductor device is an n-channel device and the second semiconductor device is a p-channel device.
11 . The electronic device of claim 7 , wherein the second width is at least 50% less than the first width.
12 . The electronic device of claim 7 , wherein an imaginary horizontal plane at least partially passes through each of the first and second bodies of semiconductor material.
13 . The electronic device of claim 7 , further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board.
14 . An integrated circuit comprising:
a first semiconductor nanoribbon or nanowire extending in a first direction from a first source or drain region to a second source or drain region, the first semiconductor nanoribbon or nanowire having a first width in a second direction different from the first direction;
a first subfin beneath the first semiconductor nanoribbon or nanowire and having the first width;
a second semiconductor nanoribbon or nanowire extending in the first direction from a third source or drain region to a fourth source or drain region, the second semiconductor nanoribbon or nanowire having a second width in a second direction that is less than the first width;
a second subfin beneath the second semiconductor nanoribbon or nanowire and having the first width; and
a gate structure extending in the second direction over the first semiconductor nanoribbon or nanowire and the second semiconductor nanoribbon or nanowire.
15 . The integrated circuit of claim 14 , wherein the first semiconductor device is an n-channel device and the second semiconductor device is a p-channel device.
16 . The integrated circuit of claim 14 , wherein the second width is at least 50% less than the first width.
17 . The integrated circuit of claim 14 , wherein an imaginary horizontal plane extending along the first and second directions at least partially passes through each of the first and second semiconductor nanoribbons or nanowires.
18 . The integrated circuit of claim 14 , wherein sidewalls of the first subfin are collinear with the sidewalls of the first semiconductor nanoribbon or nanowire, and sidewalls of the second subfin are not collinear with the sidewalls of the second semiconductor nanoribbon or nanowire.
19 . The integrated circuit of claim 1 , wherein the second subfin has an inwardly curved top surface between a first portion of the second subfin that has the second width and a second portion of the second subfin that has the first width.
20 . The integrated circuit of claim 14 , wherein the second subfin has an inwardly curved top surface between a first portion of the second subfin that has the second width and a second portion of the second subfin that has the first width.