Semiconductor substrate manufacturing method and semiconductor substrate

1 . A manufacturing method of a semiconductor substrate, comprising:

providing a base substrate;

forming a semiconductor stack layer comprising a first semiconductor layer, a second semiconductor layer and a third semiconductor layer on the base substrate by a physical vapor deposition process, comprising:

forming the first semiconductor layer on the base substrate with the base substrate at a first temperature, wherein a material of the first semiconductor layer is a first oxide semiconductor material;

forming the second semiconductor layer directly on the first semiconductor layer, wherein a material of the second semiconductor layer is a second oxide semiconductor material; and

forming the third semiconductor layer, wherein a material of the third semiconductor layer is a third oxide semiconductor material;

performing a patterning process on the semiconductor stack layer, such that the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are respectively patterned into a seed layer, a first channel layer and a second channel layer, wherein the seed layer, the first channel layer and the second channel layer constitute a channel stack layer;

forming a gate electrode and a gate insulating layer on the base substrate; and

forming a source electrode and a drain electrode on the base substrate formed with the channel stack layer, wherein the source electrode and the drain electrode are electrically connected to the channel stack layer,

wherein the second channel layer is located between the gate electrode and the first channel layer, the first oxide semiconductor material is different from the third oxide semiconductor material, and the first channel layer and the seed layer are crystalline phase layers,

wherein both the first oxide semiconductor material and the second oxide semiconductor material are capable of forming crystalline phases at a second temperature, the second temperature is less than or equal to 40° C., and the first temperature is greater than or equal to 100° C.,

wherein the first oxide semiconductor material of the first semiconductor layer is the same as the second oxide semiconductor material of the second semiconductor layer, and the second semiconductor layer is formed at the second temperature,

wherein a thickness of the second semiconductor layer is four to eight times of a thickness of the first semiconductor layer,

wherein both the first semiconductor layer and the second semiconductor layer are formed as crystalline phases.

2 . The manufacturing method according to claim 1 , wherein the gate electrode is located between the channel stack layer and the base substrate, and the first semiconductor layer is formed on a surface of the third semiconductor layer away from the base substrate.

3 . The manufacturing method according to claim 1 , further comprising: forming an insulating layer on the base substrate, wherein the insulating layer is located between the first semiconductor layer and the base substrate, the channel stack layer is located between the gate electrode and the base substrate, and the first semiconductor layer is formed on a surface of the insulating layer away from the base substrate.

4 . The manufacturing method according to claim 1 , wherein the channel stack layer has a bottom surface facing the base substrate and a side surface, both the bottom surface and the side surface are planar surfaces, and a first included angle between the bottom surface and the side surface is 20° to 70°.

5 . The manufacturing method according to claim 1 , wherein the channel stack layer has a bottom surface facing the base substrate and a side surface, the side surface comprises a first sub-side surface and a second sub-side surface, all of the bottom surface, the first sub-side surface and the second sub-side surface are planar surfaces, a second included angle between the bottom surface and the first sub-side surface is 50° to 80°, a third included angle between the second sub-side surface and the bottom surface is 20° to 70°, and the second included angle is different from the third included angle.

6 . The manufacturing method according to claim 1 , wherein the third semiconductor layer is an amorphous phase layer.

7 . The manufacturing method according to claim 1 , wherein an electron mobility of the third semiconductor layer is greater than electron mobilities of the first semiconductor layer and the second semiconductor layer.

8 . The manufacturing method according to claim 1 , wherein a band gap Eg1 of the second channel layer, a band gap Eg2 of the seed layer and a band gap Eg3 of the first channel layer satisfy: Eg1<Eg2≤Eg3;

a conduction band bottom energy level Ec1 of the second channel layer, a conduction band bottom energy level Ec2 of the seed layer and a conduction band bottom energy level Ec3 of the first channel layer satisfy: |Ec1|>|Ec2|≥|Ec3; and

a valence band top energy level Ev1 of the second channel layer, a valence band top energy level Ev2 of the seed layer and a valence band top energy level Ev3 of the first channel layer satisfy: |Ev1|<|Ev2|≤|Ev3|.

9 . The manufacturing method according to claim 1 , wherein a thickness of the seed layer is 50 angstroms to 100 angstroms.

10 . The manufacturing method according to claim 1 , wherein the first temperature is greater than 120° C.

11 . The manufacturing method according to claim 1 , wherein each of the first oxide semiconductor material and the second oxide semiconductor material comprises two or more metal elements selected from the group consisting of In, Ga, Zn and Sn.

12 . The manufacturing method according to claim 11 , wherein each of the first oxide semiconductor material and the second oxide semiconductor material is IGZO material, wherein a ratio of an atomic number of In to a sum of atomic numbers of In, Ga and Zn is 7%-14%; a ratio of an atomic number of Ga to a sum of atomic numbers of In, Ga and Zn is 20%-40%; and a ratio of an atomic number of Zn to a sum of atomic numbers of In, Ga and Zn is 50%-70%.

13 . The manufacturing method according to claim 11 , wherein each of the first oxide semiconductor material and the second oxide semiconductor material is IGZO material, wherein a ratio of an atomic number of In to a sum of atomic numbers of In, Ga and Zn is 35%-50%; a ratio of an atomic number of Ga to a sum of atomic numbers of In, Ga and Zn is 10%-40%; and a ratio of an atomic number of Zn to a sum of atomic numbers of In, Ga and Zn is 20%-40%.

14 . The manufacturing method according to claim 1 , wherein the third semiconductor layer comprises a first semiconductor sublayer and a second semiconductor sublayer, the first semiconductor sublayer is between the gate electrode and the second semiconductor sublayer, the first semiconductor sublayer is a crystalline phase layer, and the second semiconductor sublayer is an amorphous phase layer,

the gate electrode is located between the channel stack layer and the base substrate, and the first semiconductor layer is formed on a surface of the second semiconductor sublayer away from the base substrate.

15 . The manufacturing method according to claim 14 , wherein the third semiconductor layer further comprises a third semiconductor sublayer, the third semiconductor sublayer is located between the gate electrode and the first semiconductor sublayer, and the third semiconductor layer is a crystalline phase layer.

16 . The manufacturing method according to claim 1 , wherein for a same etchant, a ratio of an etching rate of the third semiconductor layer to an etching rate of the second semiconductor layer is in a range of 0.2 to 5.