Booster circuit for semiconductor memory device
The semiconductor wiring has the N-well layer of the impurity layer in the P substrate formed in the region where the poly wiring and P substrate face each other, wherein the N-well layer is electrically floating, is not used as a circuit element, and does not input or output signals. The semiconductor wiring is used as a transmission path of a high voltage signal, and used for a wiring that transmits a write signal of information at the memory cell array of the semiconductor memory device.
1 . A memory device, comprising:
a memory cell array having a plurality of memory cells each connected to a word line and a bit line;
a booster circuit configured to supply a write voltage to the word line; and
a semiconductor wiring provided in the booster circuit,
wherein the semiconductor wiring includes:
a first semiconductor region of a first conductivity type;
a floating layer provided in the first semiconductor region, and including impurities of a second conductivity type;
an insulating layer formed on at least an entire upper surface of the floating layer and an upper surface of the first semiconductor region around the floating layer; and
at least one semiconductor wiring layer provided on the insulating layer, and facing the floating layer via the insulating layer, the semiconductor wiring layer having a capacitive coupling with the floating layer via the insulating layer,
wherein the insulating layer directly faces the first semiconductor region and the floating layer.
2 . The memory device according to claim 1 , wherein when the first conductivity type is a P type, the floating layer is an N-type semiconductor layer or N-well layer of the second conductivity type.
3 . The memory device according to claim 1 , wherein a width of the floating layer is equal to or less than a width of the semiconductor wiring layer.
4 . The memory device according to claim 1 , wherein when the floating layer has a rectangular cross-sectional shape, the floating layer is formed facing at least one surface of the semiconductor wiring layer.
5 . The memory device according to claim 1 , wherein the semiconductor wiring layer is formed of a semiconductor material including poly silicon.
6 . The semiconductor device according to claim 1 , wherein the write voltage is a voltage for writing information in a memory cell array.
7 . The semiconductor device according to claim 1 , wherein the floating layer forms an island impurity layer in a charged up state by an arbitrary voltage being applied to a floating potential from an outside.
8 . The semiconductor device according to claim 1 , wherein the floating layer has impurities of a pentavalent element containing phosphorus (P) or arsenic (As) introduced.
9 . The semiconductor device according to claim 1 , wherein the insulating layer has a thickness that suppresses a tunnel current by preventing an electric field generated by the write voltage applied to the semiconductor wiring layer from exceeding 5-6 MV/cm.
10 . The semiconductor device according to claim 1 , wherein the insulating layer has a thickness of 40 nm or more.
11 . The semiconductor device according to claim 1 , wherein the semiconductor wiring layer is used in the semiconductor wiring in combination with a metal wiring.
12 . The semiconductor device according to claim 1 , wherein
the booster circuit includes:
a first diode including a first anode and a first cathode, the first anode electrically connected to a supply terminal of an outside voltage;
a second diode including a second anode and a second cathode, the second anode electrically connected to the first cathode;
a third diode including a third anode and a third cathode, the third anode electrically connected to the second cathode, and the third cathode electrically connected to the semiconductor wiring;
a first capacitor including a first node and second node, the first node electrically connected to the first cathode and the second anode, and the second node supplied with a clock signal; and
a second capacitor including a third node and a fourth node, the third node electrically connected to the second cathode and the third anode, and the fourth node supplied with an inverted clock signal.
13 . The semiconductor device according to claim 1 , further comprising:
an operation amplifier including a first input node supplied with a monitor potential, a second input node supplied with a reference potential, and an output node electrically connected to a supply terminal of the booster circuit;
a first resistor including a fifth node and a sixth node, the fifth node electrically connected to an output terminal of the booster circuit, and the sixth node electrically connected to the first input node; and
a second resistor including a seventh node and an eighth node, the seventh node electrically connected to the sixth node and first input node, and the eighth node electrically connected to a ground terminal,
wherein at least one of the first and second resistors includes the semiconductor wiring layer.
14 . The memory device according to claim 1 , wherein a center of a cross section of the semiconductor wiring layer along a short side direction is above the floating layer.
15 . The memory device according to claim 1 , wherein the semiconductor wiring is provided in an output terminal of the booster circuit.
16 . The memory device according to claim 1 , wherein one end of the semiconductor wiring is connected to the word line.