Method for forming transistor structure with a vertically grown source and drain

1 . A method for forming a transistor structure comprising:

preparing a substrate with an original surface;

using a hard mask layer to form a gate recess;

forming of a channel region comprising:

depositing a doped semiconductor layer in the gate recess;

thermal annealing the doped semiconductor layer to form the channel region underneath the gate recess; and

forming a gate dielectric layer in the gate recess;

forming a gate conductive region in the gate recess, wherein at least a portion of the gate conductive region is disposed below the original surface; and a bottom wall and sidewalls of the gate conductive region are surrounded by the gate dielectric layer; and

forming a first conductive region after the forming of the gate conductive region, wherein a bottom wall of the first conductive region is aligned with a top wall of the gate conductive region.

2 . The method according to claim 1 , wherein the hard mask layer is a nitride hard mask layer.

3 . The method according to claim 2 , wherein the forming of the first conductive region comprises:

removing the nitride hard mask layer;

etching the substrate to form a first recess; and

forming the first conductive region by a selective growth process.

4 . The method according to claim 3 , wherein the selective growth process comprises a selective epitaxy growth (SEG) method or an atomic layer deposition (ALD) method.

5 . A method for forming a transistor structure comprising:

preparing a substrate with an original surface;

using a nitride hard mask layer to form a gate recess for the gate conductive region;

forming of a channel region comprising:

depositing a p-type doped poly-silicon plug or oxide in the gate recess; and

thermal annealing the p-type doped poly-silicon plug or oxide to form the channel region underneath the gate recess;

forming a gate dielectric layer in the gate recess;

forming a gate conductive region in the gate recess, wherein at least a portion of the gate conductive region is disposed below the original surface; and a bottom wall and sidewalls of the gate conductive region are surrounded by the gate dielectric layer; and

forming a first conductive region after the forming of the gate conductive region, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

6 . A method for forming a transistor structure comprising:

preparing a substrate with an original surface;

forming a gate conductive region, wherein at least a portion of the gate conductive region is disposed below the original surface; and a bottom wall and sidewalls of the gate conductive region are surrounded by a gate dielectric layer, wherein the forming of the gate conductive region comprises:

using a first hard mask layer to form a gate recess for the gate conductive region;

forming a channel region comprising:

depositing a doped semiconductor layer in the gate recess; and

thermal annealing the doped semiconductor layer to form the channel region underneath the gate recess;

forming the gate dielectric layer in the gate recess; and

forming the gate conductive region in the gate recess;

depositing a second hard mask layer over the gate conductive region;

removing the first hard mask to reveal portion of the original surface of the substrate and etching down the revealed original surface to form a first recess; and

forming a first conductive region by a selective growth process based on the first recess, wherein a bottom wall of the first conductive region is aligned with a top wall of the gate conductive region.

7 . The method according to claim 6 , wherein the second hard mask layer comprises an edge portion outside a peripheral of the gate conductive region, and the first conductive region is limited by and not higher than the edge portion.

8 . The method according to claim 7 , wherein the selective growth process comprises a SEG method or an ALD method.

9 . A method for forming a transistor structure comprising:

preparing a substrate with an original surface;

using a hard mask oxide layer to form a gate recess for the gate conductive region;

depositing a p-type doped poly-silicon plug or oxide in the gate recess;

thermal annealing the p-type doped poly-silicon plug or oxide to form the channel region underneath the gate recess;

forming a gate dielectric layer in the gate recess;

forming a gate conductive region in the gate recess, wherein at least a portion of the gate conductive region is disposed below the original surface; and a bottom wall and sidewalls of the gate conductive region are surrounded by the gate dielectric layer; and

forming a first conductive region after the forming of the gate conductive region, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.