Silicon carbide semiconductor device
In an edge termination region, p-type regions and p − -type regions configuring a spatial modulation JTE structure are selectively provided at depth positions apart from a front surface of a semiconductor substrate. Respective bottoms of the p-type regions and the p − -type regions are at depth positions deeper from the front surface of the semiconductor substrate than is a bottom of a p-type peripheral region of a peripheral portion of an active region. An outer-side corner of the bottom of the p-type peripheral region is surrounded by an innermost one of the p-type regions and is free from contact with an n − -type drift region of the edge termination region.
1 . A silicon carbide semiconductor device, comprising:
a semiconductor substrate containing silicon carbide and having a first main surface and a second main surface that are opposite to each other, the entire first main surface being flat;
an active region provided in the semiconductor substrate;
a termination region provided in the semiconductor substrate, surrounding a periphery of the active region;
a first semiconductor region of a first conductivity type, provided in the semiconductor substrate, spanning the active region and the termination region;
a second semiconductor region of a second conductivity type, provided in the active region, between the first main surface and the first semiconductor region;
a device element structure provided in the active region, and having a pn junction between the first semiconductor region and the second semiconductor region, a current passing through the pn junction flowing through the device element structure;
a second-conductivity-type peripheral region provided between the first main surface and the first semiconductor region, between the device element structure and the termination region, the second-conductivity-type peripheral region surrounding a periphery of the device element structure;
a first electrode provided at the first main surface, the first electrode being electrically connected to the second semiconductor region and the second-conductivity-type peripheral region;
a second electrode provided at the second main surface of the semiconductor substrate, the second electrode being electrically connected to the first semiconductor region;
a plurality of second-conductivity-type withstand voltage regions provided in the first semiconductor region in the termination region, at a position apart from the first main surface in a depth direction, the plurality of second-conductivity-type withstand voltage regions being provided in a concentric shape surrounding the periphery of the active region and being apart from one another in a direction of a normal to the concentric shape; and
a voltage withstanding structure configured by the plurality of second-conductivity-type withstand voltage regions and having an overall impurity concentration of the second conductivity type, which gradually decreases in a direction from the active region to the termination region, wherein
the second-conductivity-type peripheral region has, at an outer end thereof, a step structure with a plurality of steps, each of the plurality of steps having a predetermined width in the direction of the normal the plurality of steps respectively forming a plurality of extension portions, each of the plurality of extension portions extending outwardly in the direction of the normal,
between any two of the plurality of extension portions, the one that is farther away from the first main surface in the depth direction is farther away from the end of the semiconductor substrate in the direction of the normal, the end of the semiconductor substrate being located farther from the active region than from the termination region,
bottoms of the plurality of second-conductivity-type withstand voltage regions are positioned closer than a bottom of the second-conductivity-type peripheral region to the first main surface,
upper surfaces of the plurality of second-conductivity-type withstand voltage regions are positioned at a same depth as a depth of a bottom of a first extension portion that is closest to the first main surface among the plurality of extension portions or at a depth closer than the depth of the bottom of the first extension portion to the first main surface,
a first second-conductivity-type withstand voltage region, which is an innermost one of the plurality of second-conductivity-type withstand voltage regions, is in contact with an outer-side corner of the bottom of the first extension portion or surrounds the first extension portion so as to cover the outer-side corner of the bottom of the first extension portion.
2 . The silicon carbide semiconductor device according to claim 1 , wherein the predetermined width is at least 2 μm.
3 . The silicon carbide semiconductor device according to claim 1 , wherein
the second-conductivity-type peripheral region has a portion that is closer than the voltage withstanding structure to the second main surface, and that has an impurity concentration of the second conductivity type of at most 1×10 19 /cm 3 .
4 . The silicon carbide semiconductor device according to claim 1 , wherein
the device element structure includes:
a third semiconductor region of the first conductivity type, selectively provided between the first main surface and the second semiconductor region, the third semiconductor region being electrically connected to the first electrode,
a trench that penetrates through the third semiconductor region and the second semiconductor region and reaches the first semiconductor region,
a gate insulating film provided in the trench,
a gate electrode provided in the trench, on the gate insulating film, and
a second-conductivity-type high-concentration region selectively provided between the first semiconductor region and the second semiconductor region, closer than a bottom of the trench to the second main surface, the second-conductivity-type high-concentration region having an impurity concentration that is higher than an impurity concentration of the second semiconductor region, the second-conductivity-type peripheral region includes:
a first peripheral region that is a portion of the second semiconductor region, disposed closer than the device element structure to the end of the semiconductor substrate, the end of the semiconductor substrate being located farther from the active region than from the termination region,
a second peripheral region that is a portion of the second-conductivity-type high-concentration region, disposed closer than the device element structure to the end of the semiconductor substrate, the second peripheral region being provided between and in contact with the first peripheral region and the first semiconductor region, and
a third peripheral region provided between the first main surface and the first peripheral region, the third peripheral region being in contact with the first peripheral region and having an impurity concentration that is higher than an impurity concentration of the first peripheral region,
the plurality of steps of the step structure of the second-conductivity-type peripheral region are formed so that the first peripheral region terminates closer than the third peripheral region to the device element structure, and the second peripheral region terminates closer than the first peripheral region to the device element structure,
the first extension portion of the outer end of the second-conductivity-type peripheral region is a portion of the third peripheral region, positioned closer than the first peripheral region to the end of the semiconductor substrate, and
the first second-conductivity-type withstand voltage region is in contact with an outer-side corner of a bottom of the third peripheral region or surrounds the outer-side corner of the bottom of the third peripheral region.
5 . The silicon carbide semiconductor device according to claim 1 , further comprising
another semiconductor region of the first conductivity type, provided between the first main surface and the voltage withstanding structure, the another semiconductor region having an impurity concentration that is higher than an impurity concentration of the first semiconductor region.
6 . The silicon carbide semiconductor device according to claim 4 , wherein
each of the plurality of second-conductivity-type withstand voltage regions has a carrier concentration that is equal to or greater than a carrier concentration of the second semiconductor region and lower than a carrier concentration of the second-conductivity-type high-concentration region.
7 . The silicon carbide semiconductor device according to claim 1 , wherein
the plurality of second-conductivity-type withstand voltage regions include:
a plurality of second second-conductivity-type withstand voltage regions, adjacent to the first second-conductivity-type withstand voltage region and closer than the first second-conductivity-type withstand voltage region to the end of the semiconductor substrate, the plurality of second second-conductivity-type withstand voltage regions having an impurity concentration that is a same impurity concentration as an impurity concentration of the first second-conductivity-type withstand voltage region;
a third second-conductivity-type withstand voltage region that is adjacent to the first second-conductivity-type withstand voltage region and closer than the first second-conductivity-type withstand voltage region to the end of the semiconductor substrate, the third second-conductivity-type withstand voltage region being positioned between each adjacent two of the plurality of second second-conductivity-type withstand voltage regions and extending to reach a point closer than an end of an outermost one of the plurality of second second-conductivity-type withstand voltage regions to the end of the semiconductor substrate, the third second-conductivity-type withstand voltage region having an impurity concentration that is lower than the impurity concentration of the first second-conductivity-type withstand voltage region; and
a plurality of fourth second-conductivity-type withstand voltage regions that is the rest of the plurality of second-conductivity-type withstand voltage regions excluding the first second-conductivity-type withstand voltage region, the plurality of second second-conductivity-type withstand voltage regions, and the third second-conductivity-type withstand voltage region, the plurality of fourth second-conductivity-type withstand voltage regions being adjacent to the third second-conductivity-type withstand voltage region and closer than the third second-conductivity-type withstand voltage region to the end of the semiconductor substrate, the plurality of fourth second-conductivity-type withstand voltage regions having an impurity concentration that is a same impurity concentration as the impurity concentration of the third second-conductivity-type withstand voltage region,
the voltage withstanding structure includes:
the first second-conductivity-type withstand voltage region;
the plurality of second second-conductivity-type withstand voltage regions;
the third second-conductivity-type withstand voltage region;
the plurality of fourth second-conductivity-type withstand voltage regions;
a first spatial modulation region that is disposed adjacent to the first second-conductivity-type withstand voltage region and closer than the first second-conductivity-type withstand voltage region to the end of the semiconductor substrate, the first spatial modulation region having an impurity concentration distribution that is spatially equivalent to an intermediate impurity concentration between the impurity concentration of the first second-conductivity-type withstand voltage region and the impurity concentration of the third second-conductivity-type withstand voltage region, wherein
the first spatial modulation region is configured by the plurality of second second-conductivity-type withstand voltage regions and portions of the third second-conductivity-type withstand voltage region, which are disposed adjacently to one another and repeatedly alternate with one another in a predetermined pattern; and
a second spatial modulation region that is disposed adjacent to the third second-conductivity-type withstand voltage region and closer than the third second-conductivity-type withstand voltage region to the end of the semiconductor substrate, the second spatial modulation region having an impurity concentration distribution that is spatially equivalent to an intermediate impurity concentration between the impurity concentration of the third second-conductivity-type withstand voltage region and an impurity concentration of the first semiconductor region, wherein
the second spatial modulation region is configured by the plurality of fourth second-conductivity-type withstand voltage regions and portions of the first semiconductor region, which are disposed adjacently to one another and repeatedly alternate with one another in a predetermined pattern, and
the voltage withstanding structure has the overall impurity concentration of the second conductivity type, which gradually decreases in a direction from the active region to the end of the semiconductor substrate.
8 . The silicon carbide semiconductor device according to claim 5 , wherein
the another semiconductor region of the first conductivity type, provided between the first main surface and the voltage withstanding structure, is a fourth semiconductor region, and
the silicon carbide semiconductor device further comprises
a fifth semiconductor region of the first conductivity type, provided in a surface region of the fourth semiconductor region and having an impurity concentration that is higher than the impurity concentration of the fourth semiconductor region.
9 . The silicon carbide semiconductor device according to claim 8 , further comprising
a sixth semiconductor region of the first conductivity type, provided between the first main surface and the first semiconductor region, closer to the end of the semiconductor substrate than the fourth semiconductor region, the sixth semiconductor region having an impurity concentration that is higher than the impurity concentration of the first semiconductor region, wherein
the fifth semiconductor region has a thickness that is less than a thickness of the sixth semiconductor region.
10 . The silicon carbide semiconductor device according to claim 8 , wherein
the thickness of the fifth semiconductor region is at least 0.1 μm.