First and second nanosheet transistors having respective first and second channel structures wherein a second source/drain structure of the second nanosheet transistor wraps around the ends of the second channel structures
A semiconductor device includes a substrate; a first nanosheet transistor, which is located on the substrate, that has a first inter-channel spacing and that has a thin gate oxide layer; and a second nanosheet transistor, which is located on the substrate, that has a second inter-channel spacing that is greater than the first inter-channel spacing and that has a thick gate oxide layer that is thicker than the thin gate oxide layer of the first nanosheet transistor. The second nanosheet transistor comprises channel structures and a source/drain structure that wraps around the ends of the channel structures. In embodiments, there are inner spaces at ends of the gate stacks in the first transistor, but not at the ends of the gate stacks in the second transistor.
1 . A semiconductor device comprising:
a semiconductor substrate;
a first nanosheet transistor, which is located on the substrate, that has a first inter-channel spacing and that has a gate oxide layer,
wherein the first nanosheet transistor comprises first channel structures of a first thickness between 4 nm to 8 nm; and
a second nanosheet transistor, which is located on the substrate, that has a second inter-channel spacing that is greater than the first inter-channel spacing and that has a gate oxide layer that is thicker than the gate oxide layer of the first nanosheet transistor,
wherein the second nanosheet transistor comprises second channel structures of a second thickness between 4 nm to 12 nm which is different than the first thickness, and
wherein the second nanosheet transistor comprises a second source/drain structure that wraps around the ends of the second channel structures.
2 . The semiconductor device of claim 1 , wherein the second source/drain structure directly contacts the gate oxide layer of the second nanosheet transistor, and wherein the first nanosheet transistor comprises a first source/drain structure and inner spacers that separate the first source/drain structure of the first nanosheet transistor from the gate oxide layer of the first nanosheet transistor.
3 . The semiconductor device of claim 2 , wherein a thickness of the inner spacers of the first nanosheet transistor is one-half of the first inter-channel spacing.
4 . The semiconductor device of claim 1 , wherein the first nanosheet transistor comprises a first metal gate stack and the second nanosheet transistor comprises a second metal gate stack.
5 . The semiconductor device of claim 4 , wherein the first metal gate stack comprises a first work function metal and the second metal gate stack comprises a second work function metal that is different than the first work function metal.
6 . The semiconductor device of claim 4 , wherein the first metal gate stack comprises a dielectric that includes silicon.
7 . The semiconductor device of claim 6 , wherein the dielectric of the first metal gate stack includes hafnium.
8 . The semiconductor device of claim 7 , wherein the dielectric of the first high k-metal gate stack includes silicon dioxide and hafnium dioxide.
9 . The semiconductor device of claim 4 , wherein the first high-k metal gate stack comprises a first dielectric and the second high k-metal gate stack comprises a second dielectric that includes a different oxide than is included in the first dielectric.
10 . The semiconductor device of claim 1 , wherein the first channel structures have a first length and the second channel structures have a second length that is different than the first length.
11 . The semiconductor device of claim 1 , wherein the first inter-channel spacing is between 5 nm to 15 nm, and the second inter-channel spacing is between 15 nm to 30 nm.