Seeded growth for 2D nanoribbon transistors
A transistor has multiple channel regions coupling source and drain structures, and a seed material is between one of the source or drain structures and a channel material, which includes a metal and a chalcogen. Each channel region may include a nanoribbon. A nanoribbon may have a monocrystalline structure and a thickness of a monolayer, less than 1 nm. A nanoribbon may be free of internal grain boundaries. A nanoribbon may have an internal grain boundary adjacent an end opposite the seed material. The seed material may directly contact the first of the source or drain structures, and the channel material may directly contact the second of the source or drain structures.
1 . A transistor, comprising:
a source structure and a drain structure;
a plurality of channel regions between and coupled to the source and drain structures, wherein an individual one of the channel regions comprises a first material and a second material between the first material and one of the source or drain structures, the first material comprising a metal and a chalcogen; and
a gate electrode coupled to the channel regions.
2 . The transistor of claim 1 , wherein the second material is directly on the first material and the one of the source or drain structures.
3 . The transistor of claim 1 , wherein the second material is on a sidewall of the source or drain structure.
4 . The transistor of claim 1 , wherein the second material separates the first material and the one of the source or drain structure.
5 . The transistor of claim 1 , wherein the first material is in direct contact with a second of the source or drain structures.
6 . The transistor of claim 1 , wherein the first material comprises the metal and the chalcogen in a crystalline structure.
7 . The transistor of claim 6 , wherein an individual one of the channel regions comprises a grain boundary adjacent the second of the source or drain structures, distal the second material.
8 . The transistor of claim 1 , wherein the first material in an individual one of the channel regions has a thickness of less than 1 nm.
9 . The transistor of claim 1 , wherein the metal is tungsten or molybdenum.
10 . The transistor of claim 1 , wherein the second material comprises tungsten or molybdenum.
11 . An integrated circuit (IC) device, comprising:
a power supply coupled to an IC die by a substrate; and
a transistor on the IC die, the transistor comprising:
a source structure coupled to a drain structure by a plurality of channel regions, wherein an individual one of the channel regions comprises a first material, the first material comprising a metal and a chalcogen, and a second material is between one of the source and drain structures and an individual one of the channel regions; and
a gate structure adjacent the channel regions.
12 . The IC device of claim 11 , wherein the second material is on a sidewall of the source or drain structure.
13 . The IC device of claim 12 , wherein the first material directly contacts the second material, the source structure, and the drain structure.
14 . The IC device of claim 13 , wherein the first material in an individual one of the channel regions has a thickness of less than 1 nm.
15 . A method, comprising:
receiving a stack of first and second layers over a substrate;
creating one or more first voids on a first side of the first layers by removing first portions of the first layers and retaining second portions of the first layers;
depositing a first material in the first voids, wherein the first material adjoins the second portions;
creating one or more second voids adjacent the first material by removing the second portions; and
forming one or more channel regions of a second material in the second voids, wherein the second material comprises a metal and a chalcogen, and the second material adjoins the first material.
16 . The method of claim 15 , wherein forming a channel region comprises forming a nanoribbon of the second material.
17 . The method of claim 15 , further comprising coupling a gate structure to one or more channel regions.
18 . The method of claim 17 , wherein coupling the gate structure to one or more channel regions comprises creating one or more third voids between the channel regions and forming a gate dielectric in the third voids.
19 . The method of claim 15 , wherein the metal is tungsten or molybdenum.
20 . The method of claim 15 , wherein the first material comprises tungsten or molybdenum.