IP Library Granted Patent US 12696508
Granted Patent B2
US 12696508 · App. 18/357,175 · Granted Jul 28, 2026

SiC semiconductor substrate and fabrication method of the SiC semiconductor substrate

Inventors: Makoto Takamura (Kyoto, JP); Takuji Maekawa (Kyoto, JP); Mitsuru Morimoto (Kyoto, JP); Noriyuki Masago (Kyoto, JP); Takayasu Oka (Kyoto, JP)
Assignee: ROHM CO., LTD.
H10D62/8325C30B29/36H10D62/40H10D62/882H10P14/3206H10P14/3208H10P14/3246H10P14/3408H10P14/3456H10P14/3822H10D8/60
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Quick Facts
Patent No.
US 12696508
App. No.
18/357,175
Granted
Jul 28, 2026
Kind
B2
Abstract

A semiconductor substrate disclosed herein includes: an SiC single crystal substrate; a graphene layer disposed on an Si plane of the SiC single crystal substrate; an SiC epitaxial growth layer disposed above the SiC single crystal substrate via the graphene layer; and a polycrystalline Si layer disposed on an Si plane of the SiC epitaxial growth layer. The semiconductor substrate may include a graphite substrate or an silicon substrate disposed on a polycrystalline Si layer. The semiconductor substrate may include an SiC polycrystalline growth layer disposed on a C plane of the SiC epitaxial growth layer.

Claims (17)

1 . A semiconductor substrate comprising:

an SiC single crystal substrate;

a graphene layer disposed on an Si plane of the SiC single crystal substrate;

an SiC epitaxial growth layer disposed above the SiC single crystal substrate via the graphene layer and having an Si plane that is a surface on which a device is formed; and

a polycrystalline layer disposed on an Si plane of the SiC epitaxial growth layer.

2 . The semiconductor substrate according to claim 1 , wherein the polycrystalline layer comprises a polycrystalline Si layer or a polycrystal SiC layer.

3 . The semiconductor substrate according to claim 2 , further comprising a graphite substrate or a silicon substrate disposed on the polycrystalline layer.

4 . The semiconductor substrate according to claim 3 , further comprising an SiC polycrystalline growth layer disposed on a C plane of the SiC epitaxial growth layer.

5 . The semiconductor substrate according to claim 4 , wherein the SiC epitaxial growth layer comprises a highly doped layer having a higher impurity concentration than a layer of the SiC epitaxial growth layer that is on a plane in contact with the SiC polycrystalline growth layer.

6 . The semiconductor substrate according to claim 1 , further comprising a graphite substrate or a silicon substrate disposed on the polycrystalline layer.

7 . The semiconductor substrate according to claim 6 , further comprising an SiC polycrystalline growth layer disposed on a C plane of the SiC epitaxial growth layer.

8 . The semiconductor substrate according to claim 7 , wherein the SiC epitaxial growth layer comprises a highly doped layer having a higher impurity concentration than a layer of the SiC epitaxial growth layer that is on a plane in contact with the SiC polycrystalline growth layer.

9 . The semiconductor substrate according to claim 2 , further comprising an SiC polycrystalline growth layer disposed on a C plane of the SiC epitaxial growth layer.

10 . The semiconductor substrate according to claim 9 , wherein the SiC epitaxial growth layer comprises a highly doped layer having a higher impurity concentration than a layer of the SiC epitaxial growth layer that is on a plane in contact with the SiC polycrystalline growth layer.

11 . The semiconductor substrate according to claim 1 , wherein the graphene layer comprises a single-layer structure or multi-layer laminated structure of graphene.

12 . The semiconductor substrate according to claim 1 , further comprising an SiC polycrystalline growth layer disposed on a C plane of the SiC epitaxial growth layer.

13 . The semiconductor substrate according to claim 12 , wherein the SiC epitaxial growth layer comprises a highly doped layer having a higher impurity concentration than a layer of the SiC epitaxial growth layer that is on a plane in contact with the SiC polycrystalline growth layer.