Work-function metal in transistors and method forming same

1 . A method comprising:

forming a dummy gate stack over a semiconductor region;

forming a source/drain region on a side of the dummy gate stack, wherein the source/drain region is of n-type;

removing the dummy gate stack to form a trench;

forming a gate dielectric layer extending into the trench and on the semiconductor region;

depositing a first work-function layer over the gate dielectric layer, wherein the first work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum;

depositing a second work-function layer between the gate dielectric layer and the first work-function layer, wherein the second work-function layer is a p-type work-function layer;

depositing a conductive filling layer over the first work-function layer; and

performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.

2 . The method of claim 1 , wherein the forming the gate dielectric layer comprises depositing a high-k dielectric layer.

3 . The method of claim 2 , wherein the second work-function layer is over and contacting the high-k dielectric layer.

4 . The method of claim 1 , wherein the depositing the second work-function layer comprises depositing a material selected from the group consisting of titanium nitride, tantalum nitride, and tungsten.

5 . The method of claim 1 , wherein the gate stack is formed aside of the source/drain region.

6 . The method of claim 1 , wherein the metal in the first work-function layer comprises elemental metal atoms.

7 . The method of claim 1 , wherein the depositing the first work-function layer comprises depositing a ruthenium layer.

8 . The method of claim 7 , wherein the ruthenium layer has a ruthenium atomic percentage greater than about 90 percent.

9 . The method of claim 1 , wherein the depositing the first work-function layer comprises depositing a molybdenum layer.

10 . The method of claim 1 , wherein the source/drain region and the gate stack are comprised in a gate-all-around transistor.

11 . An integrated circuit structure comprising:

a semiconductor region;

a source/drain region on a side of the semiconductor region; and

a gate stack over the semiconductor region, the gate stack comprising:

a high-k gate dielectric layer;

a first work-function layer over the high-k gate dielectric layer, wherein the first work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof, and wherein the first work-function layer has a mid-gap work function that is close to about 4.55 eV; and

a conductive filling layer on the first work-function layer.

12 . The integrated circuit structure of claim 11 , wherein the metal in the first work-function layer comprises elemental metal atoms.

13 . The integrated circuit structure of claim 11 , wherein the first work-function layer comprises ruthenium.

14 . The integrated circuit structure of claim 11 , wherein the first work-function layer comprises molybdenum.

15 . The integrated circuit structure of claim 11 further comprising a second work-function layer under the first work-function layer.

16 . An integrated circuit structure comprising:

a first transistor comprising:

a first semiconductor region;

a first gate spacer and a second gate spacer over the first semiconductor region; and

a first gate stack over the first semiconductor region and between the first gate spacer and the second gate spacer, the first gate stack comprising:

a first high-k dielectric layer;

a first work-function layer over and contacting the first high-k dielectric layer;

a second work-function layer over and contacting the first work-function layer, wherein the second work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof;

a source/drain region on a side of the first gate stack, wherein the source/drain region and the first work-function layer have opposite conductivity types; and

a filling-metal region over and contacting the second work-function layer.

17 . The integrated circuit structure of claim 16 further comprising a second transistor, wherein the first transistor and the second transistor are of opposite conductivity types, and wherein the second transistor comprises:

a second semiconductor region; and

a second gate stack over the second semiconductor region, the second gate stack comprising:

a second high-k dielectric layer;

a third work-function layer over and contacting the second high-k dielectric layer, wherein the first work-function layer has an n-type work function, and the third work-function layer has a p-type work function;

a fourth work-function layer over and contacting the third work-function layer, wherein the fourth work-function layer and the second work-function layer are formed of same materials; and

a second filling-metal region over and contacting the fourth work-function layer.

18 . The integrated circuit structure of claim 16 , wherein the source/drain region is of n-type, and the first work-function layer has a p-type work-function.

19 . The integrated circuit structure of claim 16 , wherein the metal in the second work-function layer has an atomic percentage greater than about 90 percent.

20 . The integrated circuit structure of claim 16 , wherein the first transistor comprises a gate-all-around transistor.