Semiconductor structure with two air gaps on two sides of a top source-drain middle-of-line contact via

1 . A semiconductor structure, comprising:

a top source/drain (S/D) middle-of-line (MOL) contact via including a first side and a second side;

a first air gap located adjacent the first side of the top S/D MOL contact via; and

a second air gap located adjacent the second side of the top S/D MOL contact via.

2 . The semiconductor structure of claim 1 , wherein the top S/D MOL contact via includes an upper portion and a lower portion and the first air gap and the second air gap are adjacent the lower portion of the top S/D MOL contact via and adjacent a backside contact of the semiconductor structure.

3 . The semiconductor structure of claim 1 , wherein the first air gap and the second air gap each include a dielectric material liner.

4 . The semiconductor structure of claim 3 , wherein the dielectric material liner closes the first air gap and the second air gap.

5 . The semiconductor structure of claim 1 , wherein the first air gap and the second air gap each have a width in a range from 2 nm to 10 nm.

6 . The semiconductor structure of claim 1 , wherein the first air gap and the second air gap each have a length in a range from 10 nm to 50 nm.

7 . The semiconductor structure of claim 1 , wherein the first air gap is located between the top S/D MOL contact via and an adjacent backside contact and the second air gap is located between the top S/D MOL contact via and an adjacent shallow trench isolation (STI).

8 . The semiconductor structure of claim 1 , further comprising:

a back end-of-line (BEOL) layer; and

a backside power rail (BPR),

wherein the top S/D MOL contact via extends between the BEOL layer and the BPR.

9 . A semiconductor structure, comprising:

a top source/drain (S/D) middle-of-line (MOL) contact via including an upper portion and a lower portion adjacent a backside contact;

a dielectric material layer located adjacent the upper portion of the top S/D MOL contact via on a first side and a second side of the top S/D MOL contact via; and

a first air gap and a second air gap located adjacent the first side and the second side of the top S/D MOL contact via along the lower portion of the top S/D MOL contact via.

10 . The semiconductor structure of claim 9 , wherein the first air gap and the second air gap each include a dielectric material liner.

11 . The semiconductor structure of claim 9 , further comprising:

a back end-of-line (BEOL) layer; and

a backside power rail (BPR), wherein the top S/D MOL contact via extends between the BEOL layer and the BPR.

12 . The semiconductor structure of claim 9 , wherein the first air gap is located between the top S/D MOL contact via and the backside contact and the second air gap is located between the top S/D MOL contact via and a shallow trench isolation (STI).

13 . The semiconductor structure of claim 9 , further comprising:

a gate cut liner located on the first side and the second side of the upper portion of the top S/D MOL contact via.

14 . The semiconductor structure of claim 9 , wherein the first air gap and the second air gap each have a width in a range from 2 nm to 10 nm.

15 . The semiconductor structure of claim 9 , wherein the first air gap and the second air gap each have a length in a range from 10 nm to 50 nm.

16 . A method of forming a semiconductor structure, the method comprising:

forming a plurality of shallow trench isolations (STIs), each of the plurality of STIs including a shallow trench isolation (STI) liner and a STI oxide fill;

forming a gate cut trench extending into at least one of the plurality of STIs, wherein the gate cut trench cuts through the STI oxide fill of the at least one of the plurality of STIs and through a bottom of the STI liner of the at least one of the plurality of STIs;

forming a gate cut liner and a gate cut fill in the gate cut trench;

forming a top source/drain (S/D) middle-of-line (MOL) contact via through the gate cut fill including a first backside contact within the top S/D MOL contact via;

selectively removing a portion of the gate cut liner and a portion of the STI oxide fill located near the portion of the gate cut liner in order to form a first cavity on a first side of the top S/D MOL contact via and a second cavity on a second side of the top S/D MOL contact via;

depositing a dielectric material liner within each of the first cavity and the second cavity in order to seal each of the first cavity and the second cavity; and

forming a first air gap adjacent the first side of the top S/D MOL contact via and a second air gap adjacent the second side of the top S/D MOL contact via.

17 . The method of claim 16 , wherein the first air gap is located between the top S/D MOL contact via and a backside contact and the second air gap is located between the top S/D MOL contact via and one of the plurality of STIs.

18 . The method of claim 16 , wherein the forming the first air gap and the forming the second air gap steps include removing portions of the gate cut liner on the first side and the second side of the top S/D MOL contact via.

19 . The method of claim 16 , further comprising:

forming a back end-of-line (BEOL) layer; and

forming a backside power rail (BPR),

wherein the top S/D MOL contact via extends between the BEOL layer and the BPR.

20 . The method of claim 16 , further comprising:

forming a plurality of metal contacts.