Coupled inductors with GaN switches in GaN 3D power block
Embodiments disclosed herein include a coupled inductor. In an embodiment, the coupled inductor comprises a first inductor and a second inductor. In an embodiment, the first inductor can be coupled to the first inductor. In an embodiment, the coupled inductor further comprises a first switch coupled to the first inductor, where the first switch comprises gallium and nitrogen, and a second switch coupled to the second inductor, where the second switch comprises gallium and nitrogen.
1 . An apparatus, comprising:
a first inductor;
a second inductor, wherein the first inductor is coupled to the second inductor;
a first semiconductor device coupled to the first inductor; and
a second semiconductor device coupled to the second inductor, wherein each of the first semiconductor device and the second semiconductor device comprises a channel layer comprising gallium and nitrogen, a source region on a first portion of the channel layer and a drain region on a second portion of the channel layer opposite the first portion, wherein a thickness of the first and second portions of the channel layer is less than a thickness of a third portion of the channel layer between the source region and the drain region, a polarization layer on the third portion of the channel layer, a passivation layer on the polarization layer, the passivation layer having a maximum lateral width along a source region to drain region direction the same as a maximum lateral width of the polarization layer along the source region to drain region direction, and a gate structure laterally between the source region and the drain region, the gate structure comprising a gate oxide that lines a gate electrode, the gate structure having an uppermost surface above an uppermost surface of the passivation layer, and the gate structure having a portion extending through the passivation layer and into but not entirely through the polarization layer, wherein the portion of the gate structure is laterally offset between the source region and the drain region.
2 . The apparatus of claim 1 , wherein the first inductor and the second inductor are formed from a first core and a second core.
3 . The apparatus of claim 2 , wherein the second core comprises:
a main section;
a first section extending out from the main section;
a second section extending out from the main section; and
a third section extending out from the main section.
4 . The apparatus of claim 3 , further comprising:
a filler between the second section and the first core, wherein the first section and the first core form the first inductor, and wherein the third section and the first core form the second inductor.
5 . The apparatus of claim 1 , wherein each of the first semiconductor device and the second semiconductor device comprise a field plate.
6 . The apparatus of claim 1 , wherein the source and drain regions of the first semiconductor device and the second semiconductor device are epitaxial semiconductor layers.
7 . The apparatus of claim 1 , wherein the first inductor and the second inductor are mechanically and electrically coupled to a printed circuit board.
8 . The apparatus of claim 7 , further comprising:
a plurality of apparatuses mechanically and electrically coupled to the printed circuit board.
9 . The apparatus of claim 8 , wherein the plurality of apparatuses comprises up to eight coupled apparatuses.
10 . An apparatus, comprising:
a first core;
a second core adjacent to the first core, wherein the second core comprises:
a main section;
a first section extending out from the main section;
a second section extending out from the main section; and
a third section extending out from the main section;
a filler between the second section and the first core;
a first switch; and
a second switch, wherein each of the first switch and the second switch comprises a channel layer comprising gallium and nitrogen, a source region on a first portion of the channel layer and a drain region on a second portion of the channel layer opposite the first portion, wherein a thickness of the first and second portions of the channel layer is less than a thickness of a third portion of the channel layer between the source region and the drain region, a polarization layer on the third portion of the channel layer, a passivation layer on the polarization layer, the passivation layer having a maximum lateral width along a source region to drain region direction the same as a maximum lateral width of the polarization layer along the source region to drain region direction, and a gate structure laterally between the source region and the drain region, the gate structure comprising a gate oxide that lines a gate electrode, the gate structure having an uppermost surface above an uppermost surface of the passivation layer, and the gate structure having a portion extending through the passivation layer and into but not entirely through the polarization layer, wherein the portion of the gate structure is laterally offset between the source region and the drain region.
11 . The apparatus of claim 10 , wherein the filler comprises iron.
12 . The apparatus of claim 10 , further comprising:
a first conductive winding around the first section; and
a second conductive winding around the third section.
13 . The apparatus of claim 10 , wherein the apparatus is to operate in a first state when a level of magnetic flux that is to pass through the filler is at an unsaturated level, and wherein the apparatus is to operate in a second state when the level of magnetic flux that is to pass through the filler is at a saturated level.
14 . The apparatus of claim 13 , wherein a first inductor and a second inductor are to operate as decoupled inductors in the first state and are to operate as a coupled inductor in the second state.
15 . The apparatus of claim 10 , wherein each of the first switch and the second switch comprise a field plate.
16 . An electronic system, comprising:
a board;
a package substrate coupled to the board;
a die coupled to the package substrate; and
a coupled inductor coupled to the board, wherein the coupled inductor comprises:
a first inductor;
a second inductor;
a first semiconductor device; and
a second semiconductor device comprising gallium and nitrogen, wherein each of the first semiconductor device and the second semiconductor device comprises a channel layer comprising gallium and nitrogen, a source region on a first portion of the channel layer and a drain region on a second portion of the channel layer opposite the first portion, wherein a thickness of the first and second portions of the channel layer is less than a thickness of a third portion of the channel layer between the source region and the drain region, a polarization layer on the third portion of the channel layer, a passivation layer on the polarization layer, the passivation layer having a maximum lateral width along a source region to drain region direction the same as a maximum lateral width of the polarization layer along the source region to drain region direction, and a gate structure laterally between the source region and the drain region, the gate structure comprising a gate oxide that lines a gate electrode, the gate structure having an uppermost surface above an uppermost surface of the passivation layer, and the gate structure having a portion extending through the passivation layer and into but not entirely through the polarization layer, wherein the portion of the gate structure is laterally offset between the source region and the drain region.
17 . The electronic system of claim 16 , further comprising a plurality of coupled inductors coupled to the board.
18 . The electronic system of claim 16 , wherein the first inductor is configured to be coupled to the second inductor.