Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes an forming a trench in a substrate, forming a gate dielectric layer on the trench, forming a gate layer on the gate dielectric layer, and annealing the gate dielectric layer and the gate layer, wherein, after the first annealing operation, the gate layer includes a molybdenum-tantalum alloy.
1 . A method of manufacturing a semiconductor device, the method comprising:
forming a trench in a substrate;
forming a gate dielectric layer on the trench;
forming a gate layer on the gate dielectric layer;
performing a first annealing, wherein performing the first annealing anneals the gate dielectric layer and the gate layer,
wherein, after the first annealing, the gate layer comprises a molybdenum-tantalum alloy;
removing an upper portion of the gate layer; and
performing a second annealing, wherein performing the second annealing anneals a lower portion of each of the gate layer and the gate dielectric layer.
2 . The method of claim 1 , wherein, after performing the first annealing, a width of the trench is greater than an electron mean free path of the gate layer.
3 . The method of claim 2 , wherein the width of the trench is greater than or equal to 2 nm and less than or equal to 20 nm.
4 . The method of claim 1 , wherein, after performing the first annealing, a resistivity of the gate layer is 30 μΩ·cm (microohm-centimeter) or less.
5 . The method of claim 1 , wherein a tantalum concentration of the gate layer is greater than or equal to 5 at % and less than or equal to 50 at %.
6 . The method of claim 1 , wherein a figure of merit of the gate layer after the first annealing is 2×10 −16 Ω·m 2 or less, and
the figure of merit of the gate layer is defined by multiplication of a resistivity of the gate layer and an electron mean free path of the gate layer.
7 . The method of claim 1 , wherein an effective work function of the gate layer after the first annealing is 4.5 eV or less.
8 . The method of claim 1 , wherein the first annealing is performed at a temperature of greater than or equal to 900° C. and less than or equal to 1200° C.
9 . The method of claim 1 , wherein a positive fixed charge is formed in the gate dielectric layer by the second annealing.
10 . The method of claim 1 , wherein a gas including nitrogen is used in the second annealing.
11 . The method of claim 1 , wherein the forming the gate layer comprises:
forming a tantalum layer on the gate dielectric layer; and
forming a molybdenum layer on the tantalum layer.
12 . The method of claim 1 , wherein the forming the gate layer comprises:
forming a molybdenum layer on the gate dielectric layer; and
forming a tantalum layer on the molybdenum layer.
13 . The method of claim 1 , wherein the forming the gate layer comprises forming a molybdenum-tantalum alloy layer on the gate dielectric layer.
14 . A method of manufacturing a semiconductor device, the method comprising:
forming a trench in a substrate;
forming a gate dielectric layer on the trench;
forming a gate layer on the gate dielectric layer;
annealing the gate dielectric layer and the gate layer;
removing an upper portion of the gate layer; and
performing plasma repair processing on a lower portion of each of the gate layer and the gate dielectric layer to repair damage caused by removing the upper portion of the gate layer,
wherein forming the gate layer comprises
forming a first tantalum layer on the gate dielectric layer, and
forming a first molybdenum layer on the first tantalum layer.
15 . The method of claim 14 , wherein the first tantalum layer and the first molybdenum layer are at least partially mixed in the annealing.
16 . The method of claim 14 , wherein the first tantalum layer reacts with the gate dielectric layer in the annealing.
17 . The method of claim 14 , wherein a positive fixed charge is formed in the gate dielectric layer in the annealing.
18 . The method of claim 14 , wherein the annealing is performed at a temperature, the temperature greater than or equal to 600° C. and less than or equal to 900° C., or greater than or equal to 900° C. and less than or equal to 1200° C.
19 . A method of manufacturing a semiconductor device, the method comprising:
forming a trench in a substrate;
forming a gate dielectric layer on the trench;
forming a gate layer on the gate dielectric layer;
annealing the gate dielectric layer and the gate layer;
removing an upper portion of the gate layer; and
performing plasma repair processing on a lower portion of each of the gate layer and the gate dielectric layer to repair damage caused by removing the upper portion of the gate layer,
wherein the forming the gate layer further comprises
forming a first molybdenum layer on the gate dielectric layer, and
forming a first tantalum layer on the first molybdenum layer.