Stacked transistor isolation features and methods of forming the same

1 . A method comprising:

patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure, the dummy nanostructure comprising doped silicon;

forming an opening between the lower semiconductor nanostructure and the upper semiconductor nanostructure by etching the doped silicon of the dummy nanostructure;

forming an isolation structure in the opening; and

depositing a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure, wherein the gate dielectric extends continuously along a first sidewall of the isolation structure, a top surface of the upper semiconductor nanostructure, a second sidewall of the isolation structure, and a bottom surface of the lower semiconductor nanostructure, the first sidewall of the isolation structure being opposite the second sidewall of the isolation structure.

2 . The method of claim 1 , further comprising:

forming a lower gate electrode on the gate dielectric and around the lower semiconductor nanostructure; and

forming an upper gate electrode on the gate dielectric and around the upper semiconductor nanostructure.

3 . The method of claim 2 , wherein the lower gate electrode comprises a p-type work function tuning layer and the upper gate electrode comprises an n-type work function tuning layer.

4 . The method of claim 1 , further comprising:

forming a lower inner spacer and an upper inner spacer adjacent, respectively, the lower semiconductor nanostructure and the upper semiconductor nanostructure;

growing a lower source/drain region adjacent the lower inner spacer; and

growing an upper source/drain region adjacent the upper inner spacer.

5 . The method of claim 4 , wherein a conductivity type of the upper source/drain region is opposite a conductivity type of the lower source/drain region.

6 . The method of claim 4 , wherein the lower inner spacer, the upper inner spacer, and the isolation structure are formed of a same dielectric material.

7 . The method of claim 1 , wherein the doped silicon of the dummy nanostructure is etched with a dry etch using chlorine gas.

8 . The method of claim 1 , wherein the dummy nanostructure has a first thickness, each of the lower semiconductor nanostructure and the upper semiconductor nanostructure have a second thickness, and the first thickness is greater than the second thickness.

9 . The method of claim 1 , wherein the dummy nanostructure has a first thickness, each of the lower semiconductor nanostructure and the upper semiconductor nanostructure have a second thickness, and the first thickness is less than the second thickness.

10 . A method comprising:

patterning a first dummy nanostructure, a second dummy nanostructure, and a semiconductor nanostructure, the first dummy nanostructure comprising a first semiconductor material, the second dummy nanostructure comprising a second semiconductor material, the semiconductor nanostructure comprising a third semiconductor material, the third semiconductor material having a lesser dopant concentration than the second semiconductor material;

recessing a sidewall of the first dummy nanostructure to form a sidewall recess;

removing the second dummy nanostructure to form an opening, wherein the sidewall of the first dummy nanostructure is recessed and the second dummy nanostructure is removed with a same etching process, the same etching process selectively etching the second semiconductor material at a faster rate than the first semiconductor material, the same etching process selectively etching the first semiconductor material at a faster rate than the third semiconductor material; and

forming an inner spacer and an isolation structure in, respectively, the sidewall recess and the opening, wherein the inner spacer and the first dummy nanostructure physically contact a bottom surface of the semiconductor nanostructure, and the isolation structure physically contacts a top surface of the semiconductor nanostructure which is opposite the bottom surface of the semiconductor nanostructure.

11 . The method of claim 10 , wherein the first semiconductor material is silicon-germanium, the second semiconductor material is doped silicon, and the third semiconductor material is doped silicon.

12 . The method of claim 11 , wherein the same etching process comprises a dry etch using chlorine gas.

13 . The method of claim 11 , wherein the second semiconductor material is doped with an n-type dopant.

14 . The method of claim 11 , wherein the second semiconductor material is doped with a p-type dopant.

15 . The method of claim 10 , wherein the second dummy nanostructure has a greater thickness than the first dummy nanostructure.

16 . The method of claim 10 , wherein the second dummy nanostructure has a lesser thickness than the first dummy nanostructure.

17 . A method comprising:

patterning a first semiconductor nanostructure, a second semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure disposed between the first semiconductor nanostructure and the second semiconductor nanostructure, the dummy nanostructure comprising silicon doped to a first dopant concentration, the first semiconductor nanostructure and the second semiconductor nanostructure each comprising silicon doped to a second dopant concentration, the first dopant concentration greater than the second dopant concentration;

forming an opening by etching the dummy nanostructure with an etching process, the etching process selectively etching the silicon doped to the first dopant concentration at a faster rate than the silicon doped to the second dopant concentration;

forming an isolation structure in the opening;

forming a first gate electrode around the first semiconductor nanostructure; and

forming a second gate electrode around the second semiconductor nanostructure, the second gate electrode physically contacting the first gate electrode.

18 . The method of claim 17 , further comprising:

growing a first source/drain region adjacent the first semiconductor nanostructure;

depositing an inter-layer dielectric on the first source/drain region; and

growing a second source/drain region on the inter-layer dielectric and adjacent the second semiconductor nanostructure.

19 . The method of claim 17 , wherein the etching process comprises a dry etch using chlorine gas.

20 . The method of claim 17 , further comprising:

depositing a gate dielectric around the isolation structure, the first semiconductor nanostructure, and the second semiconductor nanostructure, wherein the gate dielectric extends continuously along a first sidewall of the isolation structure, a top surface of the first semiconductor nanostructure, a second sidewall of the isolation structure, and a bottom surface of the second semiconductor nanostructure, the first sidewall of the isolation structure being opposite the second sidewall of the isolation structure, wherein the first gate electrode and the second gate electrode are formed on the gate dielectric.