Silicon carbide semiconductor device
A semiconductor device having a first polysilicon layer of a gate runner that is electrically connected to a gate pad via a built-in gate resistor constituted by a second polysilicon layer, and has a potential lower than that of the gate pad. The first polysilicon layer is disposed apart from a third polysilicon layer. The third polysilicon layer directly beneath the gate pad and the first polysilicon layer are apart from each other and face each other across an insulation layer in a direction parallel to a front surface of a semiconductor substrate. The surface of a portion of the insulation layer between the first and third polysilicon layers that are adjacent to each other is covered by a gate metal wiring layer of the gate runner, and is fixed to the potential of the gate metal wiring layer when pn junctions directly beneath the gate pad are reverse biased.
1 . A silicon carbide semiconductor device having a built-in gate resistor, the silicon carbide semiconductor device comprising:
a semiconductor substrate containing silicon carbide and having an active region center portion and an active region peripheral portion different from the active region center portion, the semiconductor substrate having a first main surface and a second main surface opposite to each other;
a first semiconductor region of a first conductivity type, provided in the semiconductor substrate;
a device structure provided in the active region center portion and having, at the first main surface of the semiconductor substrate, an insulated gate with a metal-oxide film-semiconductor (MOS) three-layer structure, a main current flowing through the device structure in a direction orthogonal to the first main surface of the semiconductor substrate, the insulated gate having a plurality of gate electrodes that constitute a metal of the insulated gate;
a second semiconductor region of a second conductivity type, provided in the semiconductor substrate and in the active region peripheral portion thereof, between the first main surface of the semiconductor substrate and the first semiconductor region, to thereby form a pn junction between the second semiconductor region and the first semiconductor region;
a plurality of polysilicon layers provided in the active region peripheral portion, at the first main surface of the semiconductor substrate via an insulating film, the plurality of polysilicon layers facing the second semiconductor region in a depth direction with the insulating film intervening therebetween;
an interlayer insulating film provided at the first main surface of the semiconductor substrate, the interlayer insulating film covering the device structure and the plurality of polysilicon layers;
a gate pad provided on the interlayer insulating film and electrically connected to the plurality of gate electrodes;
a first electrode provided at the first main surface of the semiconductor substrate and apart from the gate pad, the first electrode being electrically connected to the device structure and the second semiconductor region; and
a second electrode provided at the second main surface of the semiconductor substrate, wherein
the plurality of polysilicon layers includes:
a first polysilicon layer connected to the plurality of gate electrodes,
a second polysilicon layer facing the first polysilicon layer via the interlayer insulating film in a direction parallel to the first main surface of the semiconductor substrate and facing the gate pad via the interlayer insulating film in the depth direction, and
a third polysilicon layer electrically connecting the first polysilicon layer and the gate pad, the third polysilicon layer being connected in series to the plurality of gate electrodes via the first polysilicon layer, and connecting the first polysilicon layer and the second polysilicon layer, a portion of the third polysilicon layer constituting the gate resistor; and
the silicon carbide semiconductor device further includes a third electrode provided on the interlayer insulating film and fixed to a potential lower than that of the second electrode when the pn junction is reverse biased, the third electrode covering the interlayer insulating film between the first polysilicon layer and the second polysilicon layer.
2 . The silicon carbide semiconductor device according to claim 1 , further comprising
a gate metal wiring layer provided on the interlayer insulating film, and apart from the gate pad, the gate metal wiring being adjacent to the first polysilicon layer in the depth direction, wherein
the gate metal wiring layer extends from a first position thereof facing the first polysilicon layer in the depth direction to a second position thereof facing an end of the second polysilicon layer via the interlayer insulating film in the depth direction, and
the gate metal wiring layer constitutes the third electrode.
3 . The silicon carbide semiconductor device according to claim 1 , further comprising
a gate metal wiring layer provided on the interlayer insulating film, and apart from the gate pad, the gate metal wiring layer being adjacent to the first polysilicon layer in the depth direction, wherein
the gate pad extends from a first position thereof facing the second polysilicon layer via the interlayer insulating film in the depth direction to a second position thereof facing an end of the first polysilicon layer via the interlayer insulating film in the depth direction, and
the gate pad constitutes the third electrode.
4 . The silicon carbide semiconductor device according to claim 1 , wherein
in a plan view of the silicon carbide semiconductor device, the first polysilicon layer is disposed between the active region center portion and the second polysilicon layer, and
the first electrode extends from a first position thereof facing the first polysilicon layer via the interlayer insulating film in the depth direction, to a second position thereof facing an end of the second polysilicon layer, and
the first electrode constitutes the third electrode.
5 . The silicon carbide semiconductor device according to claim 1 , wherein
the potential of the third electrode is in a range of −20V to +20V.
6 . The silicon carbide semiconductor device according to claim 1 , wherein
the first polysilicon layer surrounds a periphery of the active region center portion and surrounds a periphery of the second polysilicon layer, in a plan view of the silicon carbide semiconductor device.