Semiconductor devices
A semiconductor device includes a first isolation structure extending through an upper portion of a substrate and defining a first active region, a first gate structure on the substrate, and first source/drain regions at upper portions of the first active region adjacent to the first gate structure. The first isolation structure includes an upper isolation pattern structure and a lower isolation pattern. The upper isolation pattern structure includes a first isolation pattern and a second isolation pattern covering a sidewall of the first isolation pattern. The lower isolation pattern is formed under and contacting the upper isolation pattern structure, and a width of the lower isolation pattern is greater than a width of the upper isolation pattern structure.
1 . A semiconductor device, comprising:
a substrate including a first region and a second region;
a first isolation structure extending through an upper portion of the first region of the substrate, the first isolation structure defining a first active region;
an impurity region under the first isolation structure in the substrate;
a first gate structure on the first region of the substrate, the first gate structure having a first thickness in a vertical direction perpendicular to an upper surface of the substrate;
a first source/drain region at an upper portion of the first active region adjacent to the first gate structure;
a second isolation structure extending through an upper portion of the second region of the substrate, the second isolation structure defining a second active region, and the second isolation structure having a void therein;
a second gate structure on the second region of the substrate, the second gate structure having a second thickness in the vertical direction that is less than the first thickness; and
a second source/drain region at an upper portion of the second active region adjacent to the second gate structure,
wherein the first isolation structure includes:
an upper isolation pattern structure including:
a first isolation pattern; and
a second isolation pattern covering a sidewall of the first isolation pattern, the second isolation pattern including an oxide; and
a lower isolation pattern under and contacting the upper isolation pattern structure, a sidewall of the lower isolation pattern contacting the substrate, a width of the lower isolation pattern being greater than a width of a bottom of the upper isolation pattern structure, and
wherein a width of the impurity region is less than a width of the first isolation structure.
2 . The semiconductor device as claimed in claim 1 , wherein a lower surface of the lower isolation pattern is curved and convex downwardly.
3 . The semiconductor device as claimed in claim 1 , wherein the lower isolation pattern includes a material the same as a material of the first isolation pattern.
4 . The semiconductor device as claimed in claim 1 , wherein the first and second isolation patterns and the lower isolation pattern include silicon oxide.
5 . The semiconductor device as claimed in claim 1 , wherein the impurity region is under the lower isolation pattern in the substrate.
6 . The semiconductor device as claimed in claim 5 , wherein a width of the impurity region is less than the width of the bottom of the upper isolation pattern structure.
7 . The semiconductor device as claimed in claim 1 , wherein
the second isolation structure includes a third isolation pattern.
8 . The semiconductor device as claimed in claim 7 , wherein the third isolation pattern includes a material the same as a material of the second isolation pattern.
9 . The semiconductor device as claimed in claim 7 , wherein a width of the third isolation pattern is less than the width of the upper isolation pattern structure.
10 . The semiconductor device as claimed in claim 7 , wherein a lower surface of the third isolation pattern is substantially coplanar with a lower surface of the upper isolation pattern structure.
11 . The semiconductor device as claimed in claim 7 , wherein a void or seam is formed in the third isolation pattern.
12 . The semiconductor device as claimed in claim 7 , wherein:
the first gate structure includes a first gate insulation structure and a first gate electrode stacked in a vertical direction perpendicular to an upper surface of the substrate,
the second gate structure includes a second gate insulation structure and a second gate electrode stacked in the vertical direction, and
a thickness of the first gate insulation structure in the vertical direction is greater than a thickness of the second gate insulation structure in the vertical direction.
13 . The semiconductor device as claimed in claim 1 , wherein the first gate structure and the first source/drain region forms a first transistor, and the second gate structure and the second source/drain region forms a second transistor, and
wherein the semiconductor device is configured such that a maximum of a voltage applied to the first transistor is greater than a maximum of a voltage applied to the second transistor.
14 . A semiconductor device, comprising:
a substrate including a first region, a second region and a third region;
a first isolation structure extending through an upper portion of the first region of the substrate, the first isolation structure defining a first active region;
an impurity region under the first isolation structure in the substrate;
a first gate structure on the first region of the substrate, the first gate structure having a first thickness in a vertical direction perpendicular to an upper surface of the substrate;
a first source/drain region at an upper portion of the first active region adjacent to the first gate structure;
a second isolation structure extending through an upper portion of the second region of the substrate, the second isolation structure defining a second active region, and the second isolation structure having a void therein;
a second gate structure on the second region of the substrate, the second gate structure having a second thickness in the vertical direction that is less than the first thickness;
a second source/drain region at an upper portion of the second active region adjacent to the second gate structure;
a third isolation structure extending through an upper portion of the third region of the substrate, the third isolation structure defining a third active region, and the third isolation structure having a seam therein;
a third gate structure on the third region of the substrate, the third gate structure having a third thickness in the vertical direction that is less than the second thickness; and
a third source/drain region at an upper portion of the third active region adjacent to the third gate structure,
wherein the first isolation structure includes:
an upper isolation pattern structure; and
a lower isolation pattern under and contacting the upper isolation pattern structure, a sidewall of the lower isolation pattern contacting the substrate, a width of the lower isolation pattern being greater than a width of a bottom of the upper isolation pattern structure, and
wherein a width of the impurity region is less than a width of the first isolation structure.
15 . The semiconductor device as claimed in claim 14 , wherein a width of the second isolation structure is greater than a width of the third isolation structure, and a width of a bottom of the first isolation structure is greater than the width of the bottom of the second isolation structure.
16 . The semiconductor device as claimed in claim 14 , wherein the upper isolation pattern structure includes:
a first isolation pattern; and
a second isolation pattern covering a sidewall of the first isolation pattern.
17 . The semiconductor device as claimed in claim 14 , wherein a lower surface of the lower isolation pattern is curved and convex downwardly.