Semiconductor device and method of fabricating the same
A semiconductor device includes first and second active patterns on first and second PMOS regions, two first source/drain patterns spaced apart along a first direction on the first active pattern and a first channel pattern including first semiconductor patterns between the two first source/drain patterns, and two second source/drain patterns spaced apart along the first direction on the second active pattern and a second channel pattern including second semiconductor patterns between the two second source/drain patterns. A width in a second direction of the each of the first semiconductor patterns is greater than a width of each of the second semiconductor patterns. Each of the first and second source/drain patterns includes semiconductor layers having different germanium concentrations. A number of the semiconductor layers of each of the two second source/drain patterns is greater than a number of the semiconductor layers of each of the two first source/drain patterns.
1 . A semiconductor device comprising:
a substrate that includes a first PMOS region and a second PMOS region;
a first active pattern on the first PMOS region and a second active pattern on the second PMOS region;
two first source/drain patterns and a first channel pattern between the two first source/drain patterns, the two first source/drain patterns being spaced apart along a first direction on the first active pattern, and the first channel pattern including a plurality of first semiconductor patterns stacked on the first active pattern; and
two second source/drain patterns and a second channel pattern between the two second source/drain patterns, the two second source/drain patterns being spaced apart along the first direction on the second active pattern, and the second channel pattern including a plurality of second semiconductor patterns stacked on the second active pattern,
wherein a first width in a second direction of each of the plurality of first semiconductor patterns is greater than a second width in the second direction of each of the plurality of second semiconductor patterns, the second direction intersecting the first direction,
wherein each of the two first source/drain patterns and each of the two second source/drain patterns includes a plurality of semiconductor layers having germanium concentrations that are different in an upward direction, and
wherein a number of the plurality of semiconductor layers of each of the two second source/drain patterns is greater than a number of the plurality of semiconductor layers of each of the two first source/drain patterns.
2 . The semiconductor device of claim 1 , wherein a third width in the second direction of each of the two first source/drain patterns is greater than a fourth width in the second direction of each of the two second source/drain patterns.
3 . The semiconductor device of claim 1 , wherein:
among the plurality of semiconductor layers of each of the two first source/drain patterns, a germanium concentration of an overlying semiconductor layer is greater than a germanium concentration of an underlying semiconductor layer, and
among the plurality of semiconductor layers of each of the two second source/drain patterns, a germanium concentration of an overlying semiconductor layer is greater than a germanium concentration of an underlying semiconductor layer.
4 . The semiconductor device of claim 1 , wherein:
a lowermost semiconductor layer of each of the two second source/drain patterns has a U-shaped cross-section, and
a bottom side thickness of the lowermost semiconductor layer is greater than a lateral side thickness of the lowermost semiconductor layer.
5 . The semiconductor device of claim 1 , wherein a level difference between a top surface of an uppermost one of the plurality of second semiconductor patterns included in the second channel pattern and a top surface of each of the two second source/drain patterns is above 0 nm to about 5 nm.
6 . The semiconductor device of claim 1 , wherein:
a first width in the first direction of the first channel pattern is greater than about 20 nm, and
a first width in the first direction of the second channel pattern is equal to or less than about 20 nm.
7 . The semiconductor device of claim 1 , wherein a first length in the second direction of the first channel pattern is substantially the same as a second length in the second direction of the second channel pattern.
8 . The semiconductor device of claim 1 , wherein a ratio of a bottom side thickness to a lateral side thickness of a lowermost semiconductor layer included in each of the two second source/drain patterns is greater than a ratio of a bottom side thickness to a lateral side thickness of a lowermost semiconductor layer included in each of the two first source/drain patterns.
9 . The semiconductor device of claim 1 , wherein a sidewall of each of the two first source/drain patterns and a sidewall of each of the two second source/drain patterns has an uneven embossing shape.
10 . A semiconductor device comprising:
a substrate that includes a first PMOS region and a second PMOS region;
a first active pattern on the first PMOS region and a second active pattern on the second PMOS region;
two first source/drain patterns and a first channel pattern between the two first source/drain patterns, the two first source/drain patterns being spaced apart along a first direction on the first active pattern, and the first channel pattern including a plurality of first semiconductor patterns stacked on the first active pattern; and
two second source/drain patterns and a second channel pattern between the two second source/drain patterns, the two second source/drain patterns being spaced apart along the first direction on the second active pattern, and the second channel pattern including a plurality of second semiconductor patterns stacked on the second active pattern,
wherein a first width in a second direction of each of the plurality of first semiconductor patterns is greater than a second width in the second direction of each of the plurality of second semiconductor patterns, the second direction intersecting the first direction,
wherein each of the two first source/drain patterns and each of the two second source/drain patterns includes a plurality of semiconductor layers having germanium concentrations that are different in an upward direction, and
wherein a level difference between a top surface of an uppermost one of the plurality of second semiconductor patterns included in the second channel pattern and a top surface of each of the two second source/drain patterns is above 0 nm to about 5 nm.
11 . The semiconductor device of claim 10 , wherein a thickness of each of the plurality of semiconductor layers included in the two first source/drain patterns is greater than a thickness of each of the plurality of semiconductor layers included in the two second source/drain patterns.
12 . The semiconductor device of claim 10 , wherein a number of the plurality of semiconductor layers included in the two second source/drain patterns is greater than a number of the plurality of semiconductor layers included in the two first source/drain patterns.
13 . The semiconductor device of claim 10 , wherein:
a first width in the first direction of each of the plurality of first semiconductor patterns is greater than about 20 nm, and
a first width in the first direction of each of the plurality of second semiconductor patterns is equal to or less than about 20 nm.
14 . The semiconductor device of claim 10 , wherein:
among the plurality of semiconductor layers of each of the two first source/drain patterns, a germanium concentration of an overlying semiconductor layer is greater than a germanium concentration of an underlying semiconductor layer, and
among the plurality of semiconductor layers of each of the two second source/drain patterns, a germanium concentration of an overlying semiconductor layer is greater than a germanium concentration of an underlying semiconductor layer.
15 . The semiconductor device of claim 10 , wherein:
a lowermost semiconductor layer of each of the two second source/drain patterns has a U-shaped cross-section, and
a bottom side thickness of the lowermost semiconductor layer is greater than a lateral side thickness of the lowermost semiconductor layer.