Semiconductor device structure with gate dielectric layer and method for forming the same
A method for forming a semiconductor device structure is provided. The method includes forming an isolation layer over a substrate. The method includes forming a spacer layer over the first fin, the second fin, and the isolation layer. The method includes forming a gate dielectric layer in the first trench and covering the first fin, the second fin, and the isolation layer exposed by the first trench. The method includes partially removing the gate dielectric layer to form a second trench in the gate dielectric layer and between the first fin and the second fin. The method includes forming a gate electrode in the first trench of the spacer layer and over the gate dielectric layer.
1 . A method for forming a semiconductor device structure, comprising:
forming an isolation layer over a substrate, wherein the substrate has a base, a first fin, and a second fin over the base, the isolation layer is over the base, and the first fin and the second fin are partially in the isolation layer;
forming a spacer layer over the first fin, the second fin, and the isolation layer, wherein the spacer layer has a first trench partially exposing the first fin and the second fin;
forming a gate dielectric layer in the first trench and covering the first fin, the second fin, and the isolation layer exposed by the first trench;
partially removing the gate dielectric layer to form a second trench in the gate dielectric layer and between the first fin and the second fin, wherein the gate dielectric layer is divided into a first part and a second part by the second trench, the gate dielectric layer has a thinner portion between a bottom of the second trench and the isolation layer, and the thinner portion links the first part and the second part; and
forming a gate electrode in the first trench of the spacer layer and over the gate dielectric layer, wherein the gate electrode extends along a top of the thinner portion.
2 . The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a first work function layer in the first trench of the spacer layer and over the first part of the gate dielectric layer before forming the gate electrode in the first trench of the spacer layer and over the gate dielectric layer, wherein the first work function layer is partially in the second trench of the gate dielectric layer, and the gate electrode is formed over the first work function layer.
3 . The method for forming the semiconductor device structure as claimed in claim 2 , further comprising:
forming a second work function layer in the first trench of the spacer layer and over the second part of the gate dielectric layer and the first work function layer before forming the gate electrode in the first trench of the spacer layer and over the gate dielectric layer, wherein the second work function layer is partially in the second trench of the gate dielectric layer, and the gate electrode is further formed over the second work function layer.
4 . The method for forming the semiconductor device structure as claimed in claim 3 , wherein the first work function layer and the second work function layer are in direct contact with the isolation layer.
5 . The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a first source/drain structure over the first fin; and
forming a second source/drain structure over the second fin, wherein the first source/drain structure and the second source/drain structure are formed using different epitaxial processes.
6 . The method for forming the semiconductor device structure as claimed in claim 5 , wherein the first source/drain structure and the second source/drain structure are made of different materials.
7 . The method for forming the semiconductor device structure as claimed in claim 1 , wherein the gate dielectric layer is formed to have a first sidewall portion and a second sidewall portion, each of the first sidewall portion and the second sidewall portion extends along a sidewall of the first trench, and the first sidewall portion is thinner than the second sidewall portion.
8 . The method for forming the semiconductor device structure as claimed in claim 7 , further comprising:
forming a first work function layer extending along a top and a sidewall of the first fin, wherein the first work function layer partially covers the first sidewall portion.
9 . The method for forming the semiconductor device structure as claimed in claim 8 , further comprising:
forming a second work function layer extending along a top and a sidewall of the second fin, wherein second first work function layer partially covers the first sidewall portion and the first work function layer.
10 . The method for forming the semiconductor device structure as claimed in claim 5 , wherein the thinner portion of the gate dielectric layer is between the first source/drain structure and the second source/drain structure in a top view of the gate dielectric layer, the first source/drain structure, and the second source/drain structure.
11 . A method for forming a semiconductor device structure, comprising:
providing a substrate having a base, a first fin, and a second fin over the base;
forming a spacer layer over the first fin, the second fin, and the base, wherein the spacer layer has a first trench partially exposing the first fin and the second fin;
forming a gate dielectric layer in the first trench and covering the first fin, the second fin, and the base under the first trench;
partially removing the gate dielectric layer to form a second trench in the gate dielectric layer and between the first fin and the second fin, wherein a first portion of the gate dielectric layer under the second trench is thinner than a second portion of the gate dielectric layer covering the first fin; and
forming a gate electrode in the first trench of the spacer layer and over the gate dielectric layer, wherein the gate electrode covers the first portion of the gate dielectric layer.
12 . The method for forming the semiconductor device structure as claimed in claim 11 , wherein the first portion of the gate dielectric layer under the second trench is thinner than a third portion of the gate dielectric layer covering the second fin.
13 . The method for forming the semiconductor device structure as claimed in claim 11 , wherein the gate dielectric layer conformally covers the first fin and the second fin.
14 . The method for forming the semiconductor device structure as claimed in claim 11 , wherein the gate dielectric layer has a bottom portion and a sidewall portion, the bottom portion covers the base, the sidewall portion covers an inner wall of the first trench of the spacer layer, and the second trench is in the bottom portion and the sidewall portion.
15 . The method for forming the semiconductor device structure as claimed in claim 11 , wherein the second trench of the gate dielectric layer has a straight strip shape in a top view of the gate dielectric layer.
16 . A method for forming a semiconductor device structure, comprising:
forming a first channel structure and a second channel structure over a substrate;
forming an isolation structure over the substrate, wherein a portion of the isolation structure is laterally between the first channel structure and the second channel structure;
forming a gate dielectric layer extending over sidewalls of the first channel structure and the second channel structure and the portion of the isolation structure;
partially removing the gate dielectric layer to form a trench extending towards the substrate, wherein the trench is over the portion of the isolation structure, and a thinner portion of the gate dielectric layer is between a bottom of the trench and the portion of the isolation structure; and
forming a gate electrode over the gate dielectric layer to cover the thinner portion of the gate dielectric layer after the trench is formed.
17 . The method for forming the semiconductor device structure as claimed in claim 16 , further comprising:
forming a dummy gate stack partially covering the first channel structure, the second channel structure, and the isolation structure;
forming a gate spacer along a sidewall of the dummy gate stack; and
removing the dummy gate stack after the gate spacer is formed.
18 . The method for forming the semiconductor device structure as claimed in claim 16 , further comprising:
forming a first work function layer extending along a top and a sidewall of the first channel structure, wherein the first work function layer partially covers the thinner portion of the gate dielectric layer.
19 . The method for forming the semiconductor device structure as claimed in claim 18 , further comprising:
forming a second work function layer extending along a top and a sidewall of the second channel structure, wherein the second work function layer partially covers the thinner portion of the gate dielectric layer and the first work function layer.
20 . The method for forming the semiconductor device structure as claimed in claim 19 , wherein the first work function layer and the second work function layer are in direct contact with the thinner portion of the gate dielectric layer.