Fabrication of gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer
Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the high-k dielectric layer on a second dipole material layer.
1 . An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires in a trench in a dielectric layer;
a second vertical arrangement of horizontal nanowires in the trench in the dielectric layer, the second vertical arrangement of horizontal nanowires laterally spaced apart from the first vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a conductive layer having a first portion directly on a first gate dielectric and a second portion laterally spaced apart from the first vertical arrangement of horizontal nanowires and along a first sidewall of the trench in the dielectric layer, and a conductive fill on the first and second portions of the conductive layer, the first gate dielectric comprising a high-k dielectric layer on a first dipole material layer; and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having a third portion of the conductive layer directly on a second gate dielectric and a fourth portion of the conductive layer laterally spaced apart from the second vertical arrangement of horizontal nanowires and along a second sidewall of the trench in the dielectric layer, the second sidewall laterally opposite the first sidewall, wherein the first, second, third and fourth portions of the conductive layer are continuous with one another, and the conductive fill on the third and fourth portions of the conductive layer, the second gate dielectric comprising the high-k dielectric layer on a second dipole material layer, the second dipole material layer having a different chemical composition than the first dipole material layer, wherein the second dipole layer is not included in the first gate stack, and the first dipole layer is not included in the second gate stack, wherein the first gate stack and the first vertical arrangement of horizontal nanowires are included in an NMOS device, and wherein the second gate stack and the second vertical arrangement of horizontal nanowires are included in a PMOS device.
2 . The integrated circuit structure of claim 1 , wherein the high-k dielectric layer is an HfO 2 layer.
3 . The integrated circuit structure of claim 1 , wherein the first dipole layer comprises a material selected from the group consisting of Al 2 O 3 , TiO 2 , ZrO 2 , HfO 2 , La 2 O 3 , Y 2 O 3 , MgO, SrO and Lu 2 O 3 , and the second dipole layer comprises a material selected from the group consisting of Al 2 O 3 , TiO 2 , ZrO 2 , HfO 2 , La 2 O 3 , Y 2 O 3 , MgO, SrO and Lu 2 O 3 .
4 . The integrated circuit structure of claim 1 , wherein one of the first or the second dipole layer has a thickness in the range of 1-3 Angstroms.
5 . The integrated circuit structure of claim 1 , wherein one of the first or the second dipole layer has a thickness in the range of 4-6 Angstroms.
6 . The integrated circuit structure of claim 1 , wherein the conductive layer is continuous between the first gate stack and the second gate stack.
7 . The integrated circuit structure of claim 1 , further comprising:
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires.
8 . The integrated circuit structure of claim 7 , further comprising:
a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and
a second pair of conductive contacts on the second pair of epitaxial source or drain structures.
9 . The integrated circuit structure of claim 7 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.
10 . The integrated circuit structure of claim 7 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of discrete epitaxial source or drain structures.
11 . An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires in a trench in a dielectric layer;
a second vertical arrangement of horizontal nanowires in the trench in the dielectric layer, the second vertical arrangement of horizontal nanowires laterally spaced apart from the first vertical arrangement of horizontal nanowires;
a third vertical arrangement of horizontal nanowires in the trench in the dielectric layer;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack a having a conductive layer having a first portion directly on a first gate dielectric and a second portion laterally spaced apart from the first vertical arrangement of horizontal nanowires and along a first sidewall of the trench in the dielectric layer, and a conductive fill on the first and second portions of the conductive layer, the first gate dielectric comprising a high-k dielectric layer on a first dipole material layer;
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having a third portion of the conductive layer directly on a second gate dielectric and a fourth portion of the conductive layer laterally spaced apart from the second vertical arrangement of horizontal nanowires and along a second sidewall of the trench in the dielectric layer, the second sidewall laterally opposite the first sidewall, wherein the first, second, third and fourth portions of the conductive layer are continuous with one another, and the conductive fill on the third and fourth portions of the conductive layer, the second gate dielectric comprising the high-k dielectric layer on a second dipole material layer, the second dipole material layer having a different chemical composition than the first dipole material layer, wherein the second dipole layer is not included in the first gate stack, and the first dipole layer is not included in the second gate stack, wherein the first gate stack and the first vertical arrangement of horizontal nanowires are included in an NMOS device, and wherein the second gate stack and the second vertical arrangement of horizontal nanowires are included in a PMOS device; and
a third gate stack over the third vertical arrangement of horizontal nanowires, the third gate stack having the conductive layer directly on a third gate dielectric, the third gate dielectric comprising the high-k dielectric layer and no dipole material layer.
12 . The integrated circuit structure of claim 11 , wherein the high-k dielectric layer is an HfO 2 layer.
13 . The integrated circuit structure of claim 11 , wherein the first and second dipole layers comprise a material selected from the group consisting of La 2 O 3 , Y 2 O 3 , MgO, SrO and Lu 2 O 3 .
14 . The integrated circuit structure of claim 11 , wherein the conductive layer is continuous between the first gate stack and the second gate stack, and is continuous between the second gate stack and the third gate stack.
15 . The integrated circuit structure of claim 11 , wherein the first dipole layer has a thickness in the range of 1-3 Angstroms, and wherein the second dipole layer has a thickness in the range of 4-6 Angstroms.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires in a trench in a dielectric layer;
a second vertical arrangement of horizontal nanowires in the trench in the dielectric layer, the second vertical arrangement of horizontal nanowires laterally spaced apart from the first vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having conductive layer having a first portion directly on a first gate dielectric and a second portion laterally spaced apart from the first vertical arrangement of horizontal nanowires and along a first sidewall of the trench in the dielectric layer, and a conductive fill on the first and second portions of the conductive layer, the first gate dielectric comprising a high-k dielectric layer on a first dipole material layer; and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having a third portion of the conductive layer directly on a second gate dielectric and a fourth portion of the conductive layer laterally spaced apart from the second vertical arrangement of horizontal nanowires and along a second sidewall of the trench in the dielectric layer, the second sidewall laterally opposite the first sidewall, wherein the first, second, third and fourth portions of the conductive layer are continuous with one another, and the conductive fill on the third and fourth portions of the conductive layer, the second gate dielectric comprising the high-k dielectric layer on a second dipole material layer, the second dipole material layer having a different chemical composition than the first dipole material layer, wherein the second dipole layer is not included in the first gate stack, and the first dipole layer is not included in the second gate stack, wherein the first gate stack and the first vertical arrangement of horizontal nanowires are included in an NMOS device, and wherein the second gate stack and the second vertical arrangement of horizontal nanowires are included in a PMOS device.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.