IP Library › Granted Patent US 12696535
Granted Patent B2
US 12696535 · App. 18/518,459 · Granted Jul 28, 2026

Semiconductor device

Inventors: Cheng-I Lin (Hsinchu, TW); Chun-Heng Chen (Hsinchu City, TW); Ming-Ho Lin (Taipei City, TW); Chi-On Chui (Hsinchu City, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10D84/853H10D84/0193H10D84/038H10P14/6336H10P14/6339
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Quick Facts
Patent No.
US 12696535
App. No.
18/518,459
Filed
Nov 23, 2023
Granted
Jul 28, 2026
Kind
B2
Art Unit
2891
USPC
257/401
Abstract

A semiconductor device includes at least one fin, a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the at least one fin. The second dielectric layer between the at least one fin and the first dielectric layer. A thickness of the first dielectric layer on a sidewall of the at least one fin is less than a thickness of the second dielectric layer on the sidewall of the at least one fin.

Claims (28)

1 . A semiconductor device, comprising:

at least one fin;

a first dielectric layer on the at least one fin; and

a second dielectric layer between the at least one fin and the first dielectric layer, wherein a thickness of the first dielectric layer on a sidewall of the at least one fin is less than a thickness of the second dielectric layer on the sidewall of the at least one fin, and a thickness of the first dielectric layer located on a top surface of the at least one fin is greater than a thickness of the second dielectric layer located on the top surface of the at least one fin.

2 . The semiconductor device according to claim 1 , wherein the thickness of the second dielectric layer on the sidewall of the at least one fin is substantially the same as the thickness of the second dielectric layer on the top surface of the at least one fin.

3 . The semiconductor device according to claim 1 , wherein the thickness of the first dielectric layer located on the top surface of the at least one fin is 3 to 6 times the thickness of the second dielectric layer located on the top surface of the at least one fin.

4 . The semiconductor device according to claim 1 , wherein a sidewall of the first dielectric layer is substantially flush with a sidewall of the second dielectric layer.

5 . The semiconductor device according to claim 1 , further comprising a gate covering the first dielectric layer.

6 . The semiconductor device according to claim 1 , wherein a top surface of the first dielectric layer is convex.

7 . The semiconductor device according to claim 1 , wherein the first dielectric layer has a chef hat shape or a helmet shape.

8 . The semiconductor device according to claim 1 , wherein at least a portion of the sidewall of the at least one fin is exposed by the first dielectric layer.

9 . The semiconductor device according to claim 1 , further comprising a gate dielectric layer covering the top surface of the at least one fin, wherein the gate dielectric layer has a convex top surface.

10 . A semiconductor device, comprising:

a semiconductor substrate comprising a protrusion; and

a dielectric pattern covering the protrusion, wherein a thickness of the dielectric pattern located on a sidewall of the protrusion decreases as the dielectric pattern becomes closer to the semiconductor substrate.

11 . The semiconductor device according to claim 10 , wherein a thickness of the dielectric pattern located on a top surface of the protrusion is greater than a thickness of the dielectric pattern located on the sidewall of the protrusion.

12 . The semiconductor device according to claim 10 , further comprising a dielectric layer disposed between the protrusion and the dielectric pattern.

13 . The semiconductor device according to claim 12 , wherein a thickness of the dielectric layer is substantially the same.

14 . The semiconductor device according to claim 12 , wherein a thickness of the dielectric pattern located on a top surface of the protrusion is greater than a thickness of the dielectric layer located on the top surface of the protrusions.

15 . The semiconductor device according to claim 10 , further comprising a gate covering the dielectric pattern.

16 . A semiconductor device, comprising:

a semiconductor substrate comprising at least one fin;

a first dielectric layer on the at least one fin, wherein a top surface of the first dielectric layer is convex; and

a second dielectric layer disposed between the at least one fin and the first dielectric layer, and the first dielectric layer covers a top surface of the at least one fin and the second dielectric layer continuously covers the top surface and a sidewall of the at least one fin.

17 . The semiconductor device according to claim 16 , wherein a thickness of the second dielectric layer located on the top surface of the at least one fin is substantially the same as a thickness of the second dielectric layer located on the sidewall of the at least one fin.

18 . The semiconductor device according to claim 16 , wherein a thickness of the first dielectric layer on the top surface of the at least one fin is greater than a thickness of the second dielectric layer located on the top surface of the at least one fin.

19 . The semiconductor device according to claim 16 , wherein a thickness of the first dielectric layer on the sidewall of the at least one fin is smaller than a thickness of the second dielectric layer located on the sidewall of the at least one fin.

20 . The semiconductor device according to claim 16 , wherein the first dielectric layer further covers the sidewall of the at least one fin.