Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drain
A structure including a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer. The structure further includes a first field effect transistor (FET) adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and a drain in the base semiconductor layer under the buried insulator layer. The second FET has a source and a drain over the buried insulator layer. The structure further includes a trench isolation in each of the source and the drain of the first FET, the source of the first FET surrounding the trench isolation therein and the drain of the first FET surrounding the trench isolation therein.
1 . A structure, comprising:
a trench isolation layer in a base semiconductor layer in a first region, and a semiconductor-on-insulator (SOI) substrate in a second region;
a first field effect transistor (FET) in the first region adjacent to a second FET in the second region, the first FET having a source and a drain in the base semiconductor layer under the trench isolation layer and a gate electrode over the trench isolation layer over the base semiconductor layer, the second FET having a source and a drain in a semiconductor-on-insulator (SOI) layer over a buried insulator layer of the SOI substrate; and
a deep trench isolation in each of the source and the drain of the first FET, the deep trench isolations integral to the trench isolation layer, the source of the first FET surrounding the deep trench isolation therein.
2 . The structure of claim 1 , wherein the gate electrode of the first FET overlaps both deep trench isolations in the source and the drain of the first FET.
3 . The structure of claim 1 , wherein the gate electrode of the first FET includes a high dielectric constant metal gate (HKMG) over the trench isolation layer.
4 . The structure of claim 1 , wherein the second FET includes a gate electrode including a high dielectric constant metal gate (HKMG) over the SOI layer.
5 . The structure of claim 1 , wherein the gate electrode of the first FET includes a gate dielectric layer including the trench isolation layer and at least one dielectric layer over the trench isolation layer.
6 . A structure, comprising:
a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer;
a first field effect transistor (FET) adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and a drain in the base semiconductor layer under the buried insulator layer, the second FET having a source and a drain over the buried insulator layer; and
a pair of well taps on opposing sides of the first FET, wherein at least one of the well taps is T-shaped; and
a trench isolation in each of the source and the drain of the first FET, the source of the first FET surrounding the trench isolation therein and the drain of the first FET surrounding the trench isolation therein.
7 . The structure of claim 6 , wherein one well tap is adjacent the source and the other well tap is adjacent the drain.
8 . The structure of claim 6 , further comprising a trench isolation between each respective well tap and the respective source and the respective drain.
9 . The structure of claim 6 , further comprising a gate dielectric including the buried insulator layer and vertically between the gate electrode and the base semiconductor layer.
10 . The structure of claim 9 , wherein the gate dielectric extends from one trench isolation to the other trench isolation.
11 . A method, comprising:
in a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer, forming a first field effect transistor (FET) in a first region of the SOI substrate, the first FET being adjacent to a second FET and having a gate electrode on the buried insulator layer and a source and a drain in the base semiconductor layer under the buried insulator layer, the second FET having a source and a drain over the buried insulator layer, wherein forming the first FET includes:
forming a trench isolation in each of the source and the drain of the first FET, the source of the first FET surrounding the trench isolation therein and the drain of the first FET surrounding the trench isolation therein; and
forming a pair of well taps on opposing sides of the first FET, wherein at least one of the well taps is T-shaped.
12 . The method of claim 11 , further comprising forming a second FET in a second region of the SOI substrate adjacent to and electrically isolated from the first region by:
doping the SOI layer to form the source and the drain for the second FET therein, the source and the drain of the second FET being over the buried insulator layer;
forming the gate electrode over the SOI layer between the source and the drain of the second FET.
13 . The method of claim 12 , wherein forming the gate electrode for the second FET occurs prior to forming the gate electrode for the first FET, and further comprising removing the gate electrode for the second FET from over the semiconductor region and the SOI layer in the first region prior to forming the gate electrode for the first FET.
14 . The method of claim 13 , further comprising epitaxially growing a raised semiconductor region over each of the source and the drain of the second FET.