Bond pad structure for bonding improvement
Some embodiments relate an integrated circuit (IC) including a first substrate. An interconnect structure is disposed over the first substrate. The interconnect structure includes a plurality of metal features that are stacked over one another. A lowermost metal feature of the plurality of metal features is closest to the first substrate, an uppermost metal feature of the plurality of metal features is furthest from the first substrate, and intermediate metal features are disposed between the lowermost metal feature and the uppermost metal feature. A recess extends into the interconnect structure and terminates at a bond pad. A lower surface of the bond pad directly contacts an upper surface of the lowermost metal feature.
1 . An integrated circuit (IC), comprising:
a first substrate;
a second substrate disposed over the first substrate;
a first interconnect structure disposed between the first substrate and the second substrate;
a second interconnect structure disposed between the first interconnect structure and the first substrate;
a bond pad structure including a base portion and sidewall portions extending up from outer edges of the base portion, the base portion having a lower surface in contact with a metal layer of the second interconnect structure and the sidewall portions extending along inner sidewalls of the first interconnect structure; and
a dielectric layer lining inner sidewalls of the bond pad structure, the dielectric layer terminating at a location on an upper surface of the base portion inside of the outer edge and leaving an area of the upper surface of the base portion inside of the outer edge uncovered by the dielectric layer.
2 . The IC of claim 1 , wherein the metal layer of the second interconnect structure is an uppermost metal layer of the second interconnect structure.
3 . The IC of claim 1 , wherein the second substrate includes a plurality of imaging devices.
4 . The IC of claim 3 , wherein the second substrate is arranged between a light source and the first interconnect structure, such that light from the light source is received by the plurality of imaging devices without previously passing through the first interconnect structure.
5 . The IC of claim 3 , wherein the first interconnect structure is arranged between a light source and the first substrate, such that light from the light source is received by the plurality of imaging devices before reaching the first substrate.
6 . The IC of claim 1 ,
wherein the first interconnect structure comprises: a first lowermost metal layer spaced at a first distance from a first surface of the first substrate; and a first uppermost metal layer spaced at a second distance from the first surface of the first substrate, the second distance being greater than the first distance;
wherein the second interconnect structure comprises: a second lowermost metal layer spaced at a third distance from a first surface of the second substrate; and a second uppermost metal layer spaced at a fourth distance from the first surface of the second substrate, the fourth distance being less than the third distance, wherein the second uppermost metal layer is nearer to the first lowermost metal layer than to the first uppermost metal layer.
7 . The IC of claim 6 ,
wherein the bond pad structure passes through the first interconnect structure, and the bond pad structure has a height that is greater than the fourth distance.
8 . The IC of claim 1 , further comprising:
a multi-layer passivation structure disposed over a top face of the second substrate.
9 . An integrated circuit (IC), comprising:
a second substrate;
a first substrate disposed over the second substrate;
a second interconnect structure disposed between an upper surface of the second substrate and a lower surface of the first substrate, wherein the second interconnect structure comprises a plurality of metal features that are stacked over one another,
a first interconnect structure disposed between an upper surface of the second interconnect structure and the lower surface of the first substrate,
wherein a lowermost metal feature of the plurality of metal features of the second interconnect structure is closest to the second substrate, an uppermost metal feature of the plurality of metal features of the second interconnect structure is furthest from the second substrate, and intermediate metal features of the second interconnect structure are disposed between the lowermost metal feature and the uppermost metal feature; and
a recess extending through the first substrate, through the first interconnect structure, and into the second interconnect structure and terminating at a bond pad, wherein a lower surface of the bond pad directly contacts an upper surface of the lowermost metal feature.
10 . The IC of claim 9 , wherein the second substrate comprises a plurality of imaging devices.
11 . The IC of claim 9 , wherein the bond pad extends along inner sidewalls of the first interconnect structure, and further comprising:
a dielectric layer lining inner sidewalls of the bond pad.
12 . The IC of claim 9 , wherein the bond pad comprises a base portion and an upper collar portion extending upwardly from the base portion, wherein a bottom surface of the base portion of the bond pad directly contacts the upper surface of the lowermost metal feature.
13 . The IC of claim 9 , wherein the bond pad comprises a base portion and an upper portion, wherein the base portion and the upper portion of the bond pad collectively have a generally U-shaped cross-section.
14 . The IC of claim 9 , wherein the second substrate includes a plurality of photodetectors and wherein the second substrate is arranged between a light source and the second interconnect structure.
15 . The IC of claim 9 , wherein the first substrate includes a plurality of photodetectors and is arranged between a light source and the first interconnect structure.
16 . The IC of claim 9 , wherein the recess has sidewalls that are angled at an angle of other than 90 degrees relative to an upper surface of the first substrate.
17 . An integrated circuit (IC), comprising:
a first substrate;
a second substrate disposed over the first substrate;
a first dielectric structure and multiple metal layers and via layers disposed within the first dielectric structure and arranged between the first substrate and the second substrate;
a second dielectric structure and multiple metal layers and via layers disposed within the second dielectric structure arranged between the first dielectric structure and the first substrate; and
a conductive structure including a base portion and a collar portion extending away from the base portion, the base portion of the conductive structure being in contact with a metal layer disposed within the second dielectric structure, and the collar portion extending within inner sidewalls of the first dielectric structure and extending past the metal layers and the vias of the first dielectric structure and arranged within inner sidewalls of the second substrate.
18 . The integrated circuit of claim 17 , wherein the base portion of the conductive structure is at a first height corresponding to the first dielectric structure and the collar portion of the conductive structure terminates at a second height corresponding to the second substrate.
19 . The integrated circuit of claim 17 , further comprising:
a dielectric layer lining inner sidewalls of the conductive structure.
20 . The integrated circuit of claim 19 , wherein the dielectric layer physically contacts an upper surface of the base portion of the conductive structure but leaves an inner area of the upper surface of the base portion exposed.