IP Library Granted Patent US 12696572
Granted Patent B2
US 12696572 · App. 18/745,245 · Granted Jul 28, 2026

Semiconductor sensor and methods thereof

Inventors: Yin-Kai Liao (Taipei City, TW); Jen-Cheng Liu (Hsin-Chu City, TW); Kuan-Chieh Huang (Hsinchu City, TW); Chih-Ming Hung (Changhua County, TW); Yi-Shin Chu (Hsinchu City, TW); Hsiang-Lin Chen (Hsinchu City, TW); Sin-Yi Jiang (Hsinchu City, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H10F71/121H10F39/014H10F39/18H10F77/1223
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Quick Facts
Patent No.
US 12696572
App. No.
18/745,245
Granted
Jul 28, 2026
Kind
B2
Abstract

A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.

Claims (30)

1 . A method of fabricating a semiconductor device, comprising:

forming a trench within a substrate;

forming a doped layer along sidewalls and along a bottom surface of the trench, wherein the doped layer is formed along the sidewalls and the bottom surface of the trench at the same time;

completely filling the trench with an undoped germanium layer disposed over the doped layer; and

forming an optoelectronic device within the undoped germanium layer.

2 . The method of claim 1 , wherein the trench is formed within a pixel region of the substrate.

3 . The method of claim 1 , wherein the optoelectronic device includes a photodiode.

4 . The method of claim 1 , wherein the forming the doped layer includes performing an ion implantation process into the sidewalls and the bottom surface of the trench.

5 . The method of claim 4 , further comprising prior to performing the ion implantation process, forming an oxide layer over the sidewalls and the bottom surface of the trench.

6 . The method of claim 5 , further comprising prior to filling the trench with the undoped germanium layer, removing the oxide layer.

7 . The method of claim 4 , wherein the ion implantation process forms a doped silicon (Si) layer along the sidewalls and the bottom surface of the trench.

8 . The method of claim 1 , wherein the forming the doped layer includes epitaxially growing a doped Si layer along the sidewalls and the bottom surface of the trench.

9 . The method of claim 1 , wherein the forming the doped layer includes epitaxially growing a doped germanium (Ge) layer along the sidewalls and the bottom surface of the trench.

10 . The method of claim 1 , wherein the doped layer includes at least one of a P-type material and Group VIIA material.

11 . A method, comprising:

forming a germanium layer within a trench defined in a silicon substrate;

forming an implant region along a bottom portion of the germanium layer within the trench, the implant region including a doped layer extending from a first lateral end of the trench to a second lateral end of the trench and spaced a distance from an interface between the germanium layer and a bottom surface of the trench defined by a portion of the silicon substrate, wherein the doped layer interposes respective first and second portions of the germanium layer disposed above and below the doped layer; and

after forming the implant region, forming an optical device within the germanium layer.

12 . The method of claim 11 , further comprising prior to forming the implant region, forming an oxide layer over the germanium layer.

13 . The method of claim 12 , further comprising prior to forming the optical device, removing the oxide layer.

14 . The method of claim 11 , further comprising after forming the optical device, forming contacts and multilayer interconnect features coupled to the optical device.

15 . The method of claim 11 , further comprising forming an optoelectronic circuit including the optical device disposed in a pixel region of the silicon substrate and a logic device disposed in a logic region of the silicon substrate.

16 . The method of claim 11 , wherein the implant region includes at least one of a P-type material and Group VIIA material.

17 . A semiconductor device, comprising:

an undoped germanium (Ge) layer formed over a substrate and defining a Ge-substrate interface, wherein an optical sensor is disposed within the undoped Ge layer; and

an ion-implanted Ge region spaced a distance from the Ge-substrate interface, wherein the ion-implanted Ge region includes a doped layer that interposes respective first and second portions of the undoped Ge layer disposed above and below the doped layer;

wherein an anode and a cathode of the optical sensor are embedded within the first portion of the undoped Ge layer disposed above the doped layer.

18 . The semiconductor device of claim 17 , wherein the substrate includes a silicon (Si) substrate, and wherein the Ge-substrate interface includes a Ge—Si interface.

19 . The semiconductor device of claim 17 , further comprising contacts and multilayer interconnect features coupled to the optical sensor.

20 . The semiconductor device of claim 17 , wherein the ion-implanted Ge region includes at least one of a P-type material and Group VIIA material.