IP Library Granted Patent US 12696685
Granted Patent B2
US 12696685 · App. 18/917,686 · Granted Jul 28, 2026

Power regeneration in a memory device

Inventor: Anthony D Veches (Boise, ID)
Assignee: Micron Technology, Inc.
H10N19/00H10N10/01H10N10/17H10W40/28H10D48/366H10N10/13H10W42/405
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Quick Facts
Patent No.
US 12696685
App. No.
18/917,686
Granted
Jul 28, 2026
Kind
B2
Abstract

A memory device comprises multiple memory dice arranged vertically in a stack of memory dice and at least one thermoelectric die contacting the bulk silicon layer of at least one of the memory dice of the multiple memory dice. Each memory die of the multiple memory dice includes an active circuitry layer that includes memory cells of a memory array and a bulk silicon layer. The thermoelectric die is configured to one or both of reduce heat from the memory die when a current is applied to terminals of the thermoelectric die and generate a voltage at the terminals of the thermoelectric die when heat from the memory die is applied to the thermoelectric die.

Claims (25)

1 . A memory system comprising:

multiple memory dice arranged in a stack of memory dice, wherein at least one memory die of the multiple memory dice includes an active circuitry layer that includes memory cells and a bulk silicon layer contacting the active layer on a first layer surface;

at least one Peltier element configured to reduce heat of the at least one memory die when a current is applied to the at least one Peltier element;

a temperature sensor configured to produce a temperature signal representative of temperature of the memory cells of the memory die; and

wherein the at least one memory die includes current drive circuitry configured to apply current to the Peltier element when the temperature signal indicates that the temperature of the memory cells exceeds a first threshold temperature and stop the current to the Peltier element when the temperature signal indicates that the temperature is less than a second threshold temperature that is less than the first threshold temperature.

2 . The memory system of claim 1 , wherein the at least one Peltier element is formed on a second layer surface of the bulk silicon layer.

3 . The memory system of claim 1 , wherein the at least one Peltier element is included in a thermoelectric die contacting the at least one memory die.

4 . The memory system of claim 3 , wherein the thermoelectric die contacts more than one memory die of the multiple memory dice.

5 . The memory system of claim 3 , including a heat sink coupled to the at least one thermoelectric die.

6 . The memory die of claim 1 , wherein the bulk silicon layer has a sidewall surface and the peltier-Peltier element contacts the sidewall surface of the silicon of the bulk silicon layer.

7 . The memory system of claim 1 ,

wherein the at least one Peltier element includes multiple Peltier elements with a Peltier element contacting each memory die of the multiple memory dice; and

wherein each memory die of the multiple memory dice includes:

a temperature sensor configured to produce a temperature signal representative of temperature of the memory cells of the memory die; and

a controller configured to initiate applying the current to the peltier-Peltier element according to the temperature signal.

8 . The memory system of claim 1 , wherein the Peltier element includes multiple alternating regions of p-type conductivity and n-type conductivity connected in series as a string of p-n regions.

9 . The memory system of claim 8 , including:

a heat sink; and

wherein the string of p-n regions is included in a thermoelectric die, the thermoelectric die is coupled to the heat sink by an electrically insulating layer and a layer of heat interfacing layer.

10 . The memory system of claim 8 , including:

wherein the regions of p-type conductivity and the regions of n-type conductivity are arranged on a second layer surface of the bulk silicon layer; and

wherein the regions of p-type conductivity are connected to the regions of n-type conductivity using an electric shunt to form the string of p-n regions on the second layer surface of the bulk silicon layer.

11 . The memory system of claim 1 ,

wherein the multiple memory dice are arranged vertically with each memory die of the multiple memory dice laterally offset from an adjacent memory die with a portion of the memory die exposed to air; and

wherein the at least one Peltier element includes multiple Peltier elements with a peltier element contacting each memory die of the multiple memory dice, and the Peltier element of each memory die extends to the exposed portion of the memory die.