Resistive memory device with enhanced local electric field and methods of forming the same

1 . A resistive memory device, comprising:

a bottom electrode comprising a barrier layer and a conductive fill portion, wherein the barrier layer forms a bottom surface and a side surface of the bottom electrode;

a dielectric material layer laterally surrounding the bottom electrode, wherein the bottom electrode includes a portion that protrudes above an upper surface of the dielectric material layer;

a switching layer over the bottom electrode, the switching layer comprising a first horizontal portion over the upper surface of the dielectric material layer, a second horizontal portion directly contacting an upper surface of the bottom electrode, and a first vertical portion directly contacting the barrier layer on the side surface of the bottom electrode between the first horizontal portion and the second horizontal portion of the switching layer, wherein a line segment having a first endpoint on the upper surface of the dielectric material layer and a second endpoint on the side surface of the bottom electrode and extending in a vertical direction substantially perpendicular to the upper surface of the dielectric material layer intersects the switching layer;

a top electrode over the switching layer, the top electrode comprising a first horizontal portion over the first horizontal portion of the switching layer, a second horizontal portion over the second horizontal portion of the switching layer, and a first vertical portion over the first vertical portion of the switching layer between the first horizontal portion and the second horizontal portion of the top electrode; and

a conductive via over the top electrode and contacting the first horizontal portion, the second horizontal portion and the first vertical portion of the top electrode, wherein the portion of the bottom electrode that protrudes above the upper surface of the dielectric material layer has a tapered side surface that defines a reentrant portion adjacent to the side surface of the bottom electrode, wherein the reentrant portion comprises a volume surrounding the bottom electrode within which a vertical line segment extending from the upper surface of the dielectric material layer contacts either the side surface or a corner portion where the side surface meets the upper surface of the bottom electrode,

wherein an upper portion of the barrier layer extends above an upper surface of the conductive fill portion, and the switching layer directly contacts the upper portion of the barrier layer on two opposite sides of the upper portion of the barrier layer.

2 . The resistive memory device of claim 1 , wherein the switching layer comprises a solid-state dielectric material that is switchable between a High Resistance State (HRS) and a Low Resistance State (LRS).

3 . The resistive memory device of claim 1 , wherein:

the first vertical portion of the switching layer extends at an oblique angle, θ 1 , with respect to the first horizontal portion of the switching layer, and

the first vertical portion of the top electrode extends at an oblique angle, θ 2 , with respect to the first horizontal portion of the top electrode, and θ 1 and θ 2 are both <90°.

4 . The resistive memory device of claim 1 , wherein the dielectric material layer comprises a first dielectric material layer, the resistive memory device further comprising a second dielectric material layer over the first dielectric material layer and laterally surrounding the conductive via.

5 . The resistive memory device of claim 4 , wherein the second dielectric material layer contacts the first horizontal portion of the top electrode.

6 . The resistive memory device of claim 5 , further comprising a passivation layer between the first dielectric material layer and the second dielectric material layer, the passivation layer contacting an upper surface and a side surface of the top electrode and a side surface of the switching layer and laterally surrounding the conductive via.

7 . The resistive memory device of claim 6 , wherein the passivation layer comprises at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and silicon oxycarbide (SiOC).

8 . The resistive memory device of claim 1 , wherein the bottom electrode comprises a raised outer portion, a recessed central portion, and an interior side surface between the raised outer portion and the recessed central portion, the second horizontal portion of the switching layer extending over the raised outer portion of the bottom electrode.

9 . The resistive memory device of claim 8 , wherein:

the switching layer comprises a third horizontal portion over the recessed central portion of the bottom electrode, and a second vertical portion over the interior side surface of the bottom electrode between the second horizonal portion and the third horizontal portion of the switching layer, and

the top electrode comprises a third horizontal portion over the third horizontal portion of the switching layer, and a second vertical portion over the second vertical portion of the switching layer.

10 . The resistive memory device of claim 9 , wherein:

the second vertical portion of the switching layer extends at an oblique angle, θ 3 , with respect to the third horizontal portion of the switching layer,

the second vertical portion of the top electrode extends at an oblique angle, θ 5 , with respect to the third horizontal portion of the top electrode, and wherein θ 3 and θ 5 are both >90°.

11 . A resistive memory device, comprising:

a bottom electrode embedded in a dielectric material layer, the bottom electrode having an outer portion that projects above an upper surface of the dielectric material layer and a central portion that is recessed relative to the outer portion, wherein an upper surface of a conductive fill portion of the bottom electrode is coplanar with the upper surface of the dielectric material layer;

a layer stack over the bottom electrode, the layer stack comprising a switching layer and a top electrode over the switching layer; and

a conductive via contacting the top electrode of the layer stack and comprising a lower portion extending below a horizontal plane containing an upper surface of the bottom electrode and laterally surrounding the outer portion of the bottom electrode, wherein the lower portion of the conductive via contacts the top electrode below the horizontal plane containing the upper surface of the bottom electrode.

12 . The resistive memory device of claim 11 , wherein the outer portion of the bottom electrode comprises a barrier layer, and the central portion comprises the conductive fill portion of the bottom electrode.

13 . The resistive memory device of claim 1 , wherein a portion of the conductive via laterally surrounds a portion of the bottom electrode.

14 . The resistive memory device of claim 12 , wherein the layer stack extends over the upper surface of the dielectric material layer, over an outer surface, an upper surface and an interior side surface of the barrier layer, and over an upper surface of the conductive fill portion of the bottom electrode.

15 . A resistive memory device, comprising:

a bottom electrode comprising a side surface, an upper surface and a corner portion between the side surface and the upper surface;

a dielectric material layer laterally surrounding the bottom electrode, wherein the bottom electrode comprises a conductive fill portion having an upper surface that is coplanar with an upper surface of the dielectric material layer;

a non-planar layer stack comprising a switching layer and a top electrode over the side surface, the upper surface and the corner portion of the bottom electrode; and

a conductive via contacting the non-planar layer stack, wherein a portion of the conductive via laterally surrounds a portion of the bottom electrode and the portion of the conductive via laterally surrounding the portion of the bottom electrode contacts the top electrode.

16 . The resistive memory device of claim 15 , wherein the bottom electrode comprises a tapered side surface, and a portion of the conductive via extends vertically beneath the corner portion of the bottom electrode.

17 . The resistive memory device of claim 15 , wherein the corner portion of the bottom electrode is located where the side surface of the bottom electrode meets the upper surface of the bottom electrode.

18 . The resistive memory device of claim 15 , wherein the bottom electrode comprises an exterior side surface and an interior side surface, the corner portion of the bottom electrode is located between the exterior side surface and the interior side surface, and the upper surface of the bottom electrode is vertically recessed with respect to the corner portion of the bottom electrode.

19 . The resistive memory device of claim 15 , further comprising a passivation layer contacting an upper surface and a side surface of the top electrode and a side surface of the switching layer and laterally surrounding the conductive via.