IP Library Granted Patent US 12696693
Granted Patent B2
US 12696693 · App. 17/534,156 · Granted Jul 28, 2026

Manufacturing method of a SiC wafer with residual stress control

Inventors: Ruggero Anzalone (Viagrande, IT); Francesco La Via (Catania, IT)
Assignee: STMicroelectronics S.r.l.
H10P14/3408H10P14/274H10P14/3438H10P72/0616H10P14/6339
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Quick Facts
Patent No.
US 12696693
App. No.
17/534,156
Granted
Jul 28, 2026
Kind
B2
Abstract

A production process of a SiC wafer carried out in a same reaction chamber includes forming, on a support, a first SiC layer. The support is separated from the first SiC layer. A second SiC layer is grown on the first SiC layer, which includes introducing into the reaction chamber a precursor in the gaseous phase of a first dopant having a first electrical conductivity to generate a first stress in the second SiC layer, and introducing into the reaction chamber a precursor in the gaseous phase of a second dopant having a second electrical conductivity opposite to the first electrical conductivity, to generate a second stress in the second SiC layer that is opposite to, and balances, the first stress. The SiC wafer is thus without effects of warpage.

Claims (33)

1 . A production process of a silicon-carbide (SiC) wafer carried out in a same reaction chamber, comprising:

forming a first SiC layer on a substrate, the substrate having a first end suspended by a first support and a second end suspended by a second support, the first end being opposite the second end along a first direction, a center of the substrate being exposed from the first and second supports, the first and second supports each having a first dimension along the first direction greater than a second dimension transverse to the first direction;

removing a first portion of the substrate from the first SiC layer by at least partially melting the substrate, the first portion being a continuous portion extending entirely from the first end to the second end along the first direction; and

growing a second SiC layer on a first surface of the first SiC layer opposite the substrate, the second SiC layer entirely covering the first surface, wherein the growing the second SiC layer includes:

introducing into the reaction chamber a precursor in gaseous phase of a first dopant having a first electrical conductivity to generate a first stress in the second SiC layer;

introducing into the reaction chamber a precursor in gaseous phase of a second dopant having a second electrical conductivity opposite to the first electrical conductivity to generate a second stress in the second SiC layer that is opposite to the first stress; and

removing a second portion of the substrate, the second portion being a residual portion remaining after removal of the first portion, completely by etching from the first SiC layer.

2 . The process according to claim 1 , wherein the melting the substrate is carried out by heating the reaction chamber up to a temperature that is at least equal to a melting temperature of the substrate, and less than a melting temperature of the first SiC layer.

3 . The process according to claim 1 , wherein a thickness of the second SiC layer is greater than a thickness of the first SiC layer.

4 . The process according to claim 1 , wherein the first SiC layer is a 3C-SiC layer.

5 . The process according to claim 1 , wherein the second SiC layer is a 3C-SiC layer.

6 . The process according to claim 1 , wherein the precursor of the first dopant is nitrogen (N 2 ).

7 . The process according to claim 1 , wherein the precursor of the second dopant is trimethylaluminium (TMA).

8 . The process according to claim 1 , wherein the precursor of the second dopant is introduced into the reaction chamber with a flow, expressed in sccm, having a value in the range of 0.01% and 1% of a flow, expressed in sccm, of the precursor of the first dopant.

9 . The process according to claim 1 , wherein the precursor of the first dopant is introduced into the reaction chamber to generate, in the second SiC layer, a concentration of the first dopant that is one order of magnitude greater than a respective concentration of the second dopant.

10 . The process according to claim 1 , wherein the precursor of the first dopant is introduced into the reaction chamber to generate, in the second SiC layer, a concentration of the first dopant in the range of 2·10 19 atoms/cm 3 and 6·10 19 atoms/cm 3 ,

and wherein the precursor of the second dopant is introduced into the reaction chamber to generate, in the second SiC layer, a concentration of the second dopant in the range of 1.5·10 18 atoms/cm 3 and 7·10 18 atoms/cm 3 .

11 . The process according to claim 1 , wherein the first electrical conductivity is of an N type, the second electrical conductivity is of a P type, the first stress is of a compressive type and the second stress is of a tensile type.

12 . The process according to claim 1 , wherein the forming the first SiC layer comprises:

introducing into the reaction chamber the precursor in the gaseous phase of the first dopant; and

introducing into the reaction chamber the precursor in the gaseous phase of the second dopant.

13 . The process according to claim 1 , wherein, to grow the first SiC layer, the precursor in gaseous phase of the first dopant and the precursor in gaseous phase of the second dopant are introduced into the reaction chamber simultaneously.

14 . The process according to claim 1 , wherein, to grow the second SiC layer, the precursor in gaseous phase of the first dopant and the precursor in gaseous phase of the second dopant are introduced into the reaction chamber simultaneously.

15 . The process according to claim 1 , wherein the growing the second SiC layers includes carrying out a CVD growth in the presence of the precursors of the first and second dopants.

16 . A method, comprising:

forming a seed silicon carbide (SiC) layer on a substrate in a reaction chamber, the seed SiC layer having a thickness less than 10 nm, the substrate having a first end suspended by a first support and a second end suspended by a second support, the first end being opposite the second end along a first direction, the first and second supports each having a first portion with a first thickness along a second direction transverse to the first direction and a second portion with a second thickness along the second direction greater than the first thickness, the first end of the substrate being suspended on the first portion of the first support and the second end of the substrate being suspended on the first portion of the second support;

removing a first portion of the substrate from the seed SiC layer by at least partially melting the substrate, the first portion being a continuous portion extending entirely from the first end to the second end along the first direction;

forming a second SiC layer on a first surface of the seed SiC layer, the second SiC layer entirely covering the first surface, the forming the second SiC layer including:

generating a first stress in the second SiC layer by introducing into the reaction chamber a precursor in gaseous phase of a first dopant having a first electrical conductivity; and

generating a second stress in the second SiC layer that is opposite to the first stress by introducing into the reaction chamber a precursor in gaseous phase of a second dopant having a second electrical conductivity opposite to the first electrical conductivity; and

removing a second portion of the substrate from the first SiC layer, the second portion being a residual portion remaining after removal of the first portion, completely by etching from the first SiC layer.

17 . The method of claim 16 , wherein the forming the second SiC layer further includes carrying out a CVD growth in the presence of the precursors of the first and second dopants.

18 . The method of claim 16 , wherein the first electrical conductivity is of an N type, the second electrical conductivity is of a P type, the first stress is of a compressive type and the second stress is of a tensile type.