Semiconductor device, method of testing the same, and method of designing the same

1 . A semiconductor device comprising:

a plurality of electrode pads;

a first input-output block coupled to each of the plurality of electrode pads;

a second input-output block coupled to each of the plurality of electrode pads;

a third input-output block coupled to each of the plurality of electrode pads;

a first functional block coupled to each of the plurality of electrode pads via the first input-output block;

a second functional block coupled to each of the plurality of electrode pads via the second input-output block; and

a third functional block coupled to the each of the plurality of electrode pads via the third input-output block,

wherein a first electrode pad of the plurality of electrode pads is located on the first input-output block and a second electrode pad of the plurality of electrode pads is located on the second input-output block,

wherein each of the plurality of electrode pads is shared among the first, second, and third functional blocks via the first, second, and third input-output blocks, and

wherein the first and second input-output blocks are located between the first functional block and the second functional block.

2 . The semiconductor device according to claim 1 , wherein the each of the plurality of electrode pads is formed at a position overlapping with one of the first and second input-output blocks.

3 . The semiconductor device according to claim 1 , wherein the first functional block, the second functional block, the first input-output block and the second input-output block are arranged in a region on a semiconductor chip that is located at a middle portion in a first direction and an end portion in a second direction orthogonal to the first direction.

4 . The semiconductor device according to claim 1 , wherein the first functional blocks, the second functional blocks, the first input-output block and the second input-output block are arranged in a corner portion of a semiconductor chip.

5 . The semiconductor device according to claim 1 ,

wherein the plurality of electrode pads includes a first electrode pad and a second electrode pad,

wherein the first electrode pad is formed at a at a position overlapping with one of the first and second input-output blocks, and

wherein the second electrode pad is formed at a at a position overlapping with the other of the first and second input-output blocks.

6 . The semiconductor device according to claim 1 , wherein the plurality of electrode pads is a part of a plurality of electrode pads that is formed on an entire surface of a semiconductor chip.

7 . The semiconductor device according to claim 6 ,

wherein the plurality of electrode pads that is formed on the entire surface of the semiconductor chip includes a dummy electrode pad that is not coupled to the first and second input-output blocks, and

wherein the dummy electrode pad is formed at a position overlapping with the first or second functional blocks.

8 . The semiconductor device according to claim 1 , wherein the first, second and third input-output blocks are disposed between the first functional block and the second functional block.

9 . The semiconductor device according to claim 1 , further comprising a plurality of test electrode pads that is used during testing, and

wherein each of the plurality of test electrode pads is coupled to the plurality of electrode pads.

10 . The semiconductor device according to claim 9 ,

wherein the plurality of electrode pads includes an electrode pad for signal input and an electrode pad for signal output, and

wherein the plurality of test electrode pads includes a test electrode pad that is coupled to the electrode pad for the signal input and a test electrode pad that is coupled to the electrode pad for the signal output.