IP Library Granted Patent US 12696734
Granted Patent B2
US 12696734 · App. 17/888,972 · Granted Jul 28, 2026

Patterning a semiconductor substrate

Inventors: Alexandra Krawicz (Albany, NY); Steven Grzeskowiak (Albany, NY); Eric Chih-Fang Liu (Albany, NY)
Assignee: TOKYO ELECTRON LIMITED
H10P76/4088H10P50/73G03F7/0042G03F7/094G03F7/11G03F7/2004
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Quick Facts
Patent No.
US 12696734
App. No.
17/888,972
Granted
Jul 28, 2026
Kind
B2
Abstract

A method of forming a semiconductor device, where the method includes receiving a substrate in a processing chamber, the substrate including a first patterned layer including a metal-based material; and with a gaseous etch process, trimming the first patterned layer to form a second patterned layer, the gaseous etch process including exposing the first patterned layer to an un-ionized gas including a halogen compound.

Claims (41)

1 . A method of forming a semiconductor device, the method comprising:

receiving a substrate in a processing chamber, the substrate comprising a first patterned layer comprising a metal-based material; and

with a gaseous etch process using a plasma-free un-ionized gas mixture, trimming the first patterned layer to form a second patterned layer, the gaseous etch process comprising flowing the plasma-free un-ionized gas mixture through the processing chamber to trim the first patterned layer, the plasma-free un-ionized gas mixture comprising a single process gas and an inert gas diluent, the single process gas comprising a halogen compound.

2 . The method of claim 1 , further comprising:

prior to forming the first patterned layer, forming an underlayer over the substrate; and

using the second patterned layer as an etch mask, etching the underlayer to form a third patterned layer.

3 . The method of claim 2 , wherein the first patterned layer comprises an array of lines designed to have a pitch that is a minimum pitch for a photolithography process used in forming the first patterned layer.

4 . The method of claim 1 , wherein the first patterned layer is a metal-based resist (MBR).

5 . The method of claim 4 , wherein the gaseous etch process is a descum process, the descum process reducing a count of resist residue defects.

6 . The method of claim 1 , wherein the first patterned layer is a tin-based resist.

7 . The method of claim 1 , wherein the first patterned layer has been formed using an extreme ultraviolet (EUV) lithography process.

8 . The method of claim 1 , wherein the halogen compound is hydrogen bromide.

9 . The method of claim 1 , wherein flowing the plasma-free un-ionized gas mixture through the processing chamber to trim the first patterned layer comprises exposing the first patterned layer to the plasma-free un-ionized gas mixture for a selected process duration.

10 . A method of patterning a semiconductor substrate, the method comprising:

receiving a substrate in a processing chamber, the substrate comprising a lithography stack over a layer to be patterned, the lithography stack comprising a patterned metal-based resist (MBR) layer and an underlayer below the patterned MBR layer; and

flowing, using a plasma-free process, an un-ionized gas mixture over the substrate, the un-ionized gas mixture comprising a halogen compound and an inert gas diluent, wherein a flow rate of the inert gas diluent is at least 4 times a flow rate of the halogen compound, wherein flowing the un-ionized gas mixture causes the patterned MBR layer to chemically react with the halogen compound.

11 . The method of claim 10 , further comprising:

prior to flowing the un-ionized gas mixture over the substrate, setting a temperature of the substrate at a selected ambient temperature, the selected ambient temperature being greater than or equal to −10° C. and less than or equal to 60° C.; and

controlling the temperature of the substrate during flowing the un-ionized gas mixture.

12 . The method of claim 10 , wherein the halogen compound is hydrogen bromide.

13 . The method of claim 10 , wherein the underlayer comprises a silicon-based antireflective coating (SiARC), spin-on glass (SOG), or silicon carbide.

14 . The method of claim 10 , wherein the lithography stack comprises a planarizing layer below the underlayer, the planarizing layer comprising an organic planarizing layer (OPL) or an amorphous carbon layer.

15 . The method of claim 10 , wherein the lithography stack comprises a hard mask layer disposed between the underlayer and the layer to be patterned.

16 . The method of claim 10 , further comprising:

after flowing the un-ionized gas mixture over the substrate, patterning the lithography stack to form a patterned lithography stack, wherein patterning the lithography stack comprises:

performing a pattern-transfer etch process using the patterned MBR layer as an etch mask, the pattern-transfer etch process transferring the pattern of the patterned MBR layer to the lithography stack; and

after patterning the lithography stack, patterning the layer to be patterned, wherein patterning the layer to be patterned comprises performing a pattern-transfer etch process using the patterned lithography stack as an etch mask.

17 . A method of forming a semiconductor device, the method comprising:

forming a metal-based resist (MBR) layer over a semiconductor substrate;

patterning the MBR layer using a photolithography process to form a patterned MBR layer, the patterned MBR layer comprising a line having a first linewidth;

exposing, using a plasma-free process, the patterned MBR layer to a flow of an un-ionized gas mixture to change the linewidth of the line from the first linewidth to a second linewidth, the second linewidth being less than the first linewidth, the un-ionized gas mixture comprising a single process gas and an inert gas diluent, the single process gas comprising a halogen compound; and

after exposing the patterned MBR layer to the flow of the un-ionized gas mixture, patterning a layer to be patterned, wherein the patterning the layer to be patterned comprises performing a pattern-transfer etch process using the patterned MBR layer as an etch mask.

18 . The method of claim 17 , wherein the halogen compound is hydrogen bromide.

19 . The method of claim 17 , wherein the exposing comprises exposing the patterned MBR layer to the flow of the un-ionized gas mixture for a first process duration, and wherein the method further comprises:

prior to forming the semiconductor device, obtaining a linewidth vs. process duration graph, the obtaining comprising:

processing a set of substrates using a corresponding set of process durations, each substrate being associated with a corresponding process duration;

for each substrate, measuring a linewidth of a line to obtain a set of measured linewidths; and

plotting the set of measured linewidths against the corresponding set of process durations to obtain the linewidth vs. process duration graph; and

selecting the first process duration from the obtained linewidth vs. process duration graph, the first process duration being selected to produce a desired linewidth in the linewidth vs. process duration graph.

20 . The method of claim 17 , wherein exposing the patterned MBR layer to the flow of the un-ionized gas mixture forms a chemically adsorbed layer on a surface of the patterned MBR layer.

21 . The method of claim 1 , wherein the first patterned layer comprises a line having a first linewidth, the trimming changing the linewidth of the line from the first linewidth to a second linewidth, the second linewidth being less than the first linewidth.