IP Library Granted Patent US 12696737
Granted Patent B2
US 12696737 · App. 18/192,549 · Granted Jul 28, 2026

Compressive films for large area gapfill

Inventors: Supriya Ghosh (San Jose, CA); Zeqing Shen (San Jose, CA); Susmit Singha Roy (Sunnyvale, CA); Abhijit Basu Mallick (Fremont, CA)
Assignee: Applied Materials, Inc.
H10P95/06H01J37/32816H10P14/6334H10P14/69215H01J2237/336
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Quick Facts
Patent No.
US 12696737
App. No.
18/192,549
Granted
Jul 28, 2026
Kind
B2
Abstract

Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the semiconductor processing chamber. The methods may include forming a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of greater than or about −200 MPa. The methods may include annealing the substrate at a temperature of greater than or about 700° C.

Claims (37)

1 . A semiconductor processing method comprising:

providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate defining one or more features is disposed within the semiconductor processing chamber;

forming a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a stress of greater than or about-200 MPa; and

annealing the substrate at a temperature of greater than or about 700° C.

2 . The semiconductor processing method of claim 1 , wherein the silicon-containing precursor comprises silane (SiH 4 ), disilane (Si 2 H 6 ), or trisilane (Si 3 H 8 ).

3 . The semiconductor processing method of claim 1 , wherein a temperature within the semiconductor processing chamber is maintained at less than or about 600° C. while forming the silicon-containing material.

4 . The semiconductor processing method of claim 1 , wherein a pressure within the semiconductor processing chamber is maintained at less than or about 350 T.

5 . The semiconductor processing method of claim 1 , further comprising:

providing an oxygen-containing precursor with the silicon-containing precursor.

6 . The semiconductor processing method of claim 1 , wherein the semiconductor processing chamber is maintained plasma-free while forming the silicon-containing material.

7 . The semiconductor processing method of claim 1 , wherein, subsequent to annealing the silicon-containing material, the silicon-containing material is characterized by a shrinkage of less than or about 5%.

8 . The semiconductor processing method of claim 1 , further comprising:

subsequent to forming the silicon-containing material, providing an inert precursor to the processing region of the semiconductor processing chamber;

forming plasma effluents of the inert precursor; and

contacting the silicon-containing material with the plasma effluents of the inert precursor.

9 . The semiconductor processing method of claim 8 , wherein the inert precursor comprises argon.

10 . The semiconductor processing method of claim 8 , further comprising:

providing an oxygen-containing precursor with the inert precursor.

11 . A semiconductor processing method comprising:

providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate comprising one or more features is disposed within the semiconductor processing chamber, and wherein the silicon-containing precursor comprises disilane (Si 2 H 6 );

forming a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a stress of greater than or about −200 MPa; and

annealing the substrate at a temperature of greater than or about 700° C., wherein the silicon-containing material is characterized by a shrinkage of less than or about 5%.

12 . The semiconductor processing method of claim 11 , wherein the silicon-containing material is characterized by a breakdown of greater than or about 5 MV/cm.

13 . The semiconductor processing method of claim 11 , wherein annealing the substrate comprises contacting the substrate with a nitrogen-containing precursor.

14 . The semiconductor processing method of claim 11 , further comprising:

performing a plasma treatment with an inert precursor subsequent to forming the silicon-containing material.

15 . The semiconductor processing method of claim 14 , wherein the plasma treatment is performed at a lower pressure than the forming of the silicon-containing material.

16 . The semiconductor processing method of claim 14 , wherein the inert precursor comprises argon.

17 . A semiconductor processing method comprising:

providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate defining one or more features is disposed within the semiconductor processing chamber;

forming a silicon-containing material on the substrate, wherein the silicon-containing material is characterized by a stress of greater than or about −200 MPa;

providing an inert precursor to the processing region of the semiconductor processing chamber;

forming plasma effluents of the inert precursor;

contacting the silicon-containing material with the plasma effluents of the inert precursor; and

annealing the substrate.

18 . The semiconductor processing method of claim 17 , wherein the silicon-containing material is characterized by a shrinkage of less than or about 5%.

19 . The semiconductor processing method of claim 17 , wherein a thickness of the silicon-containing material is less than or about 30 Å.