Transistor device with sinker contacts and methods for manufacturing the same

1 . A method, comprising:

providing a partially processed semiconductor wafer with a trench opening etched through a portion of a semiconductor wafer;

depositing a titanium (Ti) layer over a top surface of the semiconductor wafer and on semiconductor sidewalls and a bottom wall of the trench opening;

depositing a titanium nitride (TiN) layer on the Ti layer;

depositing a first conductive layer that partially fills the trench opening and on the TiN layer;

etching back the first conductive layer thereby removing it from over the surface of the semiconductor wafer;

depositing a second conductive layer over the top surface of the semiconductor wafer and into the trench opening; and

etching back the second conductive layer thereby removing it from over the surface of the semiconductor wafer,

wherein a portion of the Ti layer exposed by etching back the first conductive layer is converted to TiN by annealing in a nitrogen ambient prior to depositing the second conductive layer.

2 . The method of claim 1 , in which the first conductive layer and the second conductive layer are first and second chemical vapor deposited tungsten (CVD-W) layers that have a thickness of equal to or less than about 700 nm.

3 . The method of claim 2 , in which the annealing is performed at a temperature in a range of about 700° C. to 900° C.

4 . The method of claim 2 , further including annealing the second CVD-W layer at a temperature in a range of about 700° C. to 900° C. in a gas that is one selected from the group consisting essentially of nitrogen, helium, and argon.

5 . The method of claim 2 , further including:

depositing a third CVD-W layer over the surface of the semiconductor wafer and into the trench opening; and

etching back the third CVD-W layer removing it from over the surface of the semiconductor wafer.

6 . The method of claim 5 , in which the first CVD-W layer is annealed in nitrogen at a temperature in a range of 700° C. and 900° C. and in which the second and third CVD-W layers are annealed at a temperature in a range of about 700° C. and 900° C. in a gas that is one selected from nitrogen, helium, and argon.

7 . The method of claim 1 , in which a thickness of the Ti layer is in a range of about 30 nm to 70 nm and in which a thickness of the TiN layer is in a range of about 5 nm to 15 nm.

8 . A method of forming an integrated circuit, comprising:

forming a trench opening that extends into a portion of a semiconductor substrate having a top surface;

depositing a titanium (Ti) layer over the top surface and on semiconductor sidewalls of the trench opening;

depositing a titanium nitride (TiN) layer on the Ti layer;

depositing a first conductive layer on the TiN layer leaving an unfilled portion of the trench opening;

removing the first conductive layer from over the top surface, thereby exposing a portion of the Ti layer;

depositing a second conductive layer over the top surface and into the unfilled portion of the trench opening;

removing the second conductive layer from over the top surface of the semiconductor substrate; and

subsequent to removing the first conductive layer from over the top surface, annealing a remaining portion of the first conductive layer within the trench in a nitrogen ambient, thereby converting the exposed portion of the Ti layer to TiN.

9 . The method of claim 8 , in which the first conductive layer and the second conductive layer are first and second chemical vapor deposited tungsten (CVD-W) layers.

10 . The method of claim 9 , further including:

depositing a third CVD-W layer over the top surface; and

etching back the third CVD-W layer removing it from over the top surface.

11 . The method of claim 10 , in which the first CVD-W layer is annealed in nitrogen at a temperature in a range of 700° C. and 900° C. and in which the second and third CVD-W layers are annealed at a temperature in a range of about 700° C. and 900° C. in a gas that is one selected from nitrogen, helium, and argon.

12 . The method of claim 8 , in which the annealing is performed at a temperature in a range of about 700° C. to about 900° C.

13 . The method of claim 8 , in which, subsequent to removing the second conductive layer from over the top surface, a remaining portion of the second conductive layer within the trench is annealed at a temperature in a range of about 700° C. to about 900° C. in a gas that is one selected from the group consisting essentially of nitrogen, helium, and argon.

14 . The method of claim 8 , in which a thickness of the Ti layer is in a range of about 30 nm to 70 nm and in which a thickness of the TiN layer is in a range of about 5 nm to 15 nm.

15 . The method of claim 8 , in which the trench opening extends through an epitaxial semiconductor layer having a first conductivity and into a buried semiconductor layer with a greater second conductivity.

16 . A method of forming an electronic device, comprising:

forming a trench opening that extends into a portion of a semiconductor layer having a top surface, the trench opening meeting the top surface at a corner;

forming a titanium (Ti) layer over the top surface of the semiconductor layer, on semiconductor sidewalls of the trench opening, and over the corner;

depositing a titanium nitride (TiN) layer on the Ti layer;

depositing a first tungsten (W) layer over the TiN layer;

at least partially removing the W layer and the TiN layer from over the top surface, thereby exposing the Ti layer over the corner;

annealing the W layer in a nitrogen ambient thereby converting the exposed Ti layer to TiN; and

depositing a second W layer over the corner.