Semiconductor device and method
An embodiment is a method including a first dielectric layer over a first substrate, the first dielectric layer having a first metallization pattern therein. The method also includes forming a second dielectric layer over the first dielectric layer and the first metallization pattern. The method also includes forming a sacrificial pad over and extending into the second dielectric layer, the sacrificial pad being electrically coupled to a first conductive feature in the first metallization pattern. The method also includes performing a circuit probe test on the sacrificial pad. The method also includes after performing the circuit probe test, performing an etch process, the etch process removing the sacrificial pad.
1 . A method comprising:
forming a first dielectric layer over a first substrate, the first dielectric layer having a first metallization pattern therein;
forming a second dielectric layer over the first dielectric layer and the first metallization pattern;
forming a sacrificial pad over and extending into the second dielectric layer, the sacrificial pad being electrically coupled to a first conductive feature in the first metallization pattern;
performing a circuit probe test on the sacrificial pad;
after performing the circuit probe test, performing an etch process, the etch process removing the sacrificial pad; and
after removing the sacrificial pad, forming a first bond via in a third dielectric layer over the second dielectric layer and the first conductive feature, the first bond via being electrically coupled to the first conductive feature in the first metallization pattern, the third dielectric layer physically contacting the first conductive feature.
2 . The method of claim 1 further comprising:
forming a first bond pad in a fourth dielectric layer over the first bond via and the third dielectric layer, the first bond pad being electrically coupled to the first bond via.
3 . The method of claim 1 , further comprising:
forming a second bond via in the third dielectric layer and the second dielectric layer, the second bond via being electrically coupled to a second conductive feature in the first metallization pattern.
4 . The method of claim 2 , wherein the sacrificial pad extends into a first opening of the second dielectric layer to physically contact the first conductive feature, wherein the first bond via extends into a second opening of the second dielectric layer to physically contact the first conductive feature.
5 . The method of claim 4 , wherein the second opening is within the first opening.
6 . The method of claim 1 , wherein the sacrificial pad is overlapping with a second conductive feature.
7 . The method of claim 1 , wherein forming the sacrificial pad comprises;
depositing a seed layer over and extending through the second dielectric layer; and
plating a solder material on the seed layer.
8 . The method of claim 1 further comprising:
forming a first patterned mask over the first dielectric layer;
performing an etch process using the first patterned mask as a mask, the etch process forming a third opening through the first dielectric layer and partially through the first substrate;
forming a liner in the third opening;
filling the third opening with a conductive material; and
thinning the first substrate to expose a portion of the conductive material in the third opening, the conductive material extending through the first dielectric layer and the first substrate forming a through substrate via.
9 . A method comprising:
forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, the metallization patterns including a top metal layer including top metal structures;
forming a passivation layer over the top metal structures of the first interconnect structure;
forming a first opening through the passivation layer, a first top metal structure of the top metal structures being exposed through the first opening;
forming a probe pad in the first opening and over the passivation layer, the probe pad being electrically connected to the first top metal structure;
performing a circuit probe test on the probe pad, the probe pad being over and extending along a top surface of the passivation layer during the circuit probe test;
after performing the circuit probe test, removing the probe pad; and
after removing the probe pad, forming a bond pad and a bond via in dielectric layers over the passivation layer, the bond pad and bond via being electrically coupled to the first top metal structure of the top metal structures.
10 . The method of claim 9 , wherein the probe pad is overlapping with a second top metal structure.
11 . The method of claim 9 , wherein removing the probe pad comprises:
performing an etch process, the etch process removing the probe pad and exposing the first top metal structure in the first opening.
12 . The method of claim 9 , wherein the probe pad comprises a solder.
13 . The method of claim 9 further comprising:
forming a second opening through the passivation layer, the bond via being in the second opening, wherein the second opening is within the first opening.
14 . The method of claim 10 , wherein forming bond pads and bond vias in dielectric layers over the passivation layer comprises:
forming a first dielectric layer over the passivation layer;
forming a second dielectric layer over the first dielectric layer;
patterning the first and second dielectric layers to expose the first top metal structure and a second top metal structure of the top metal structures;
forming bond vias over the first and second top metal structures and in the first dielectric layer, the bond vias being electrically coupled to the first and second top metal structures; and
forming first bond pads over the bond vias and in the second dielectric layer, the first bond pads being electrically coupled to the bond vias.
15 . The method of claim 14 , wherein the first dielectric layer extends through the passivation layer and physically contacts the first top metal structure.
16 . The method of claim 14 further comprising:
direct bonding the second dielectric layer and the first bond pads to a third dielectric layer and second bond pads of a package structure, the package structure comprising a second substrate and a second interconnect structure over the second substrate, the third dielectric layer and the second bond pads being part of the second interconnect structure.
17 . The method of claim 16 further comprising
after direct bonding the second dielectric layer and the first bond pads to the third dielectric layer and the second bond pads of the package structure, forming a first redistribution structure over the first substrate, the first redistribution structure comprising dielectric layers and metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the through substrate via; and
forming a first set of conductive bumps over and electrically coupled to the first redistribution structure.
18 . The method of claim 9 , further comprising:
forming a second bond pad and a second bond via in dielectric layers over the passivation layer, the second bond pad and the second bond via being electrically coupled to a second top metal structure of the top metal structures.
19 . A structure comprising:
a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein;
a through substrate via extending through the first interconnect structure and the first substrate;
a first top metal structure and a second top metal structure in a first dielectric layer over the first interconnect structure;
a second dielectric layer over the second top metal structure and partially over the first top metal structure;
a third dielectric layer over the second dielectric layer, the third dielectric layer extending through the second dielectric layer to physically contact the first top metal structure;
a first bond via in the second and third dielectric layers over the first top metal structure, the first bond via being electrically coupled to the first top metal structure;
a first bond pad in a fourth dielectric layer over the first bond via, the first bond pad being electrically coupled to the first bond via;
a second bond via in the second and third dielectric layers over the second top metal structure, the second bond via being electrically coupled to the second top metal structure; and
a second bond pad in a fourth dielectric layer over the second bond via, the second bond pad being electrically coupled to the second bond via.
20 . The structure of claim 19 , wherein the third dielectric layer does not physically contact the second top metal structure.