Semiconductor device including metal lines having multi-layer structure

1 . A method of manufacturing a semiconductor device, the method comprising:

forming a base layer; and

forming at least one metal line on the base layer such that each of the at least one metal line comprises a 1 st metal structure and a 2 nd metal structure on the 1 st metal structure,

wherein the 1 st metal structure is patterned from an initial 1 st metal structure on which an initial sacrificial structure is formed, and the initial sacrificial structure is patterned to form at least one sacrificial structure,

wherein the 2 nd metal structure is formed on the initial 1 st metal structure at a space from which the at least one sacrificial structure is removed by entirely replacing the at least one sacrificial structure,

wherein a width of the 2 nd metal structure in a 1 st direction is formed equal to a width of the at least one sacrificial structure in the 1 st direction,

wherein the 2 nd metal structure is formed to provide an electrical connectivity to the 1 st metal structure,

wherein the 1 st direction is parallel with an upper surface of the base layer, and

wherein the 2 nd metal structure is formed through a damascene process.

2 . The method of claim 1 , wherein the 1 st metal structure is formed through a direct etching process.

3 . The method of claim 2 , wherein the 1 st metal structure is formed based on the 2 nd metal structure as a masking structure.

4 . The method of claim 1 , wherein the forming the at least one metal line comprise forming a plurality of metal lines at a same level,

wherein each of the plurality of metal lines comprises the 1 st metal structure and the 2 nd metal structure on the 1 st metal structure,

wherein the 1 st metal structures of the plurality of metal lines are formed through a direct etching process, and the 2 nd metal structures of the plurality of metal lines are formed through the damascene process, and

wherein the damascene process is performed prior to the direct etching process.

5 . The method of claim 4 , wherein the 1 st metal structures are formed based on the 2 nd metal structures as respective masking structures.

6 . The method of claim 1 , wherein the forming at least one metal line is performed such that:

the 1 st metal structure and the 2 nd metal structure have a same width in the 1 st direction; and

left and right side surfaces of the 1 st metal structure and left and right side surfaces of the 2 nd metal structure are vertically aligned or coplanar, respectively.

7 . The method of claim 1 , wherein the forming the at least one metal line comprises:

providing the 1 st metal structure formed of a material having a higher resistivity to electromigration than a material forming the 2 nd metal structure, and

providing the 2 nd metal structure formed of a material having a higher conductivity than a material forming the 1 st metal structure.

8 . The method of claim 1 , wherein the forming the at least one metal line comprises:

providing the 1 st metal structure formed of ruthenium (Ru), and

providing the 2 nd metal structure formed of copper (Cu), tungsten (W) or molybdenum (Mo).

9 . A method of manufacturing a semiconductor device, the method comprising:

forming a plurality of 1 st sacrificial structures of a dielectric material to be arranged in a 1 st direction on an initial 1 st metal structure, the plurality of 1 st sacrificial structures having a thickness extending vertically with respect to the 1 st direction;

forming a plurality of 2 nd sacrificial structures on side surfaces of the plurality of 1 st sacrificial structures such that a 2 nd sacrificial structure of the plurality of 2 nd sacrificial structures on a right side surface of a 1 st sacrificial structure of the plurality of 1 st sacrificial structures is spaced apart, by a recess, from another 2 nd sacrificial structure of the plurality of 2 nd sacrificial structures on a left side surface of another 1 st sacrificial structure of the plurality of 1 st sacrificial structures adjacent to the 1 st sacrificial structure;

removing the plurality of 1 st sacrificial structures;

filling out, along an entirety of the thickness, the recess and a space provided by the removing of the plurality of 1 st sacrificial structures with a plurality of 2 nd metal structures by a damascene process;

removing the plurality of 2 nd sacrificial structures; and

patterning the initial 1 st metal structure based on the plurality of 2 nd metal structures to form a plurality of 1 st metal structures,

wherein widths of the plurality of 2 nd metal structures in the 1 st direction are formed equal to corresponding widths of the plurality of 1 st sacrificial structures in the 1 st direction,

wherein the plurality of 2 nd metal structures remain on the plurality of 1 st metal structures without being removed, and

wherein the 1 st direction is parallel with an upper surface of the initial 1 st metal structure.

10 . The method of claim 9 , wherein a material forming the initial 1 st metal structure has a higher resistivity to electromigration than a material forming the plurality of 2 nd metal structures, and

wherein a material forming the plurality of 2 nd metal structures has a higher conductivity than a material forming the initial 1 st metal structure.

11 . The method of claim 10 , wherein the initial 1 st metal structure comprises ruthenium (Ru), and the plurality of 2 nd metal structures comprises copper (Cu), tungsten (W) or molybdenum (Mo).