Multi-metal fill with self-aligned patterning and dielectric with voids
Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
1 . A structure, comprising:
a dielectric stack on a substrate;
a metal line on the dielectric stack;
a first etch stop layer on the metal line;
a metal via through the dielectric stack;
a second etch stop layer on the metal via;
a dielectric layer over the first and second etch stop layers and in contact with a side surface of the metal via, wherein the dielectric layer comprises a void adjacent to the metal line and the metal via, and wherein a top of the void is above a horizontal interface between the metal line and the first etch stop layer; and
an other dielectric layer over a side surface of the dielectric layer, wherein the top of the void is above an upper surface of the other dielectric layer.
2 . The structure of claim 1 , wherein a side surface of the metal line and a side surface of the first etch stop layer are coplanar.
3 . The structure of claim 1 , wherein bottom surfaces of the first and second etch stop layers are coplanar.
4 . The structure of claim 1 , wherein:
the first etch stop layer comprises a first metal oxide; and
the second etch stop layer comprises a second metal oxide different from the first metal oxide.
5 . The structure of claim 1 , wherein a side surface of the dielectric layer is over a side surface of the metal line.
6 . The structure of claim 1 , wherein ratio of a volume of the void to a volume of a space between the metal line and the metal via is between about 30% and about 70%.
7 . The structure of claim 1 , wherein an interface between the other dielectric layer and the dielectric layer is below the first and second etch stop layers.
8 . A structure, comprising:
a metal line on a substrate;
a dielectric stack on the metal line;
a first conductive structure on the dielectric stack and directly above the metal line;
a first oxide layer on the first conductive structure;
a second conductive structure laterally adjacent to the first conductive structure and in contact with the metal line;
a second oxide layer on the second conductive structure;
a first dielectric layer over the first and second oxide layers, wherein a first interface between the first dielectric layer and the first conductive structure is coplanar with a second interface between the first dielectric layer and the first oxide layer; and
a second dielectric layer over the first dielectric layer, wherein a third interface between the first and second dielectric layers is parallel to the first and second interfaces.
9 . The structure of claim 8 , wherein bottom surfaces of the first and second oxide layers are coplanar.
10 . The structure of claim 8 , wherein the first and second oxide layers comprise different metallic elements from each other.
11 . The structure of claim 8 , wherein the first and second oxide layers comprise one or more of aluminum-based oxides, tungsten-based oxides, nickel-based oxides, zirconium-based oxides, cobalt-based oxides, and combinations thereof.
12 . The structure of claim 8 , wherein a side surface of the first dielectric layer is over a side surface of the first oxide layer.
13 . The structure of claim 8 , wherein the first dielectric layer comprises:
a void between the first and second conductive structures; and
a portion between the void and the first oxide layer, wherein the portion comprises a flat surface and a curved surface.
14 . The structure of claim 8 , wherein a side surface of the second dielectric layer is opposite to a side surface of the first conductive structure.
15 . A structure, comprising:
a first metal line extending in a first lateral direction;
a dielectric stack on the first metal line;
a second metal line on the dielectric stack and extending in a second lateral direction different from the first lateral direction, wherein the second metal line is directly above the first metal line;
a first etch stop layer on the second metal line;
a metal via through the dielectric stack and extending in a vertical direction, wherein the metal via is laterally adjacent to the second metal line;
a second etch stop layer on the metal via;
a first dielectric layer over the first and second etch stop layers, wherein a first interface between the first dielectric layer and the second etch stop layer is coplanar with a second interface between the first dielectric layer and the metal via; and
a second dielectric layer on the first dielectric layer, wherein a third interface between the first and second dielectric layers is below the first and second etch stop layers.
16 . The structure of claim 15 , wherein the second metal line and the metal via comprise different metallic elements from each other.
17 . The structure of claim 15 , wherein top surfaces of the first and second etch stop layers are coplanar.
18 . The structure of claim 15 , wherein the first dielectric layer comprises a void between the first and second etch stop layers, and wherein the void comprises a curved bottom surface.
19 . The structure of claim 18 , wherein a side surface of the second dielectric layer is parallel to a side surface of the first etch stop layer.
20 . The structure of claim 15 , wherein a horizontal distance between the first and second etch stop layer is substantially the same as a horizontal distance between the second metal line and the metal via.