IP Library Granted Patent US 12696745
Granted Patent B2
US 12696745 · App. 17/955,677 · Granted Jul 28, 2026

Composite contact between backside power element and source/drain region

Inventors: Koichi Motoyama (Clifton Park, NY); Alexander Reznicek (Troy, NY); Tsung-Sheng Kang (Ballston Lake, NY); Oscar van der Straten (Guilderland Center, NY)
Assignee: International Business Machines Corporation
H10W20/20H10D30/43H10D30/6729H10D30/6757H10D62/121H10D84/834H10W20/023H10W20/069H10W20/427
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Quick Facts
Patent No.
US 12696745
App. No.
17/955,677
Granted
Jul 28, 2026
Kind
B2
Abstract

A semiconductor device includes a transistor having a source/drain region and a contact disposed on the source/drain region. The semiconductor device further includes a via extending from the contact along a side of the source/drain region to a power element. The contact and the via each comprise a plurality of conductive materials.

Claims (47)

1 . A semiconductor device, comprising:

a transistor comprising a source/drain region;

a contact disposed on the source/drain region; and

a via extending from the contact along a side of the source/drain region to a power element;

wherein the contact and the via each comprise a plurality of conductive materials; and

wherein the contact comprises:

a liner layer comprising a first conductive material;

a first fill layer on a first portion of the liner layer and comprising a second conductive material; and

a second fill layer on a second portion of the liner layer and comprising a third conductive material.

2 . The semiconductor device of claim 1 , wherein the power element comprises a power rail.

3 . The semiconductor device of claim 1 , further comprising an isolation region, wherein the power element is disposed on the isolation region and the via extends through the isolation region to contact the power element.

4 . The semiconductor device of claim 1 , wherein at least a portion of the first fill layer is disposed between the second fill layer and the liner layer.

5 . The semiconductor device of claim 1 , wherein the first conductive material comprises one of tantalum, tantalum nitride and titanium nitride, the second conductive material comprises a noble metal and the third conductive material comprises one of cobalt, copper and tungsten.

6 . The semiconductor device of claim 1 , wherein the via comprises:

a liner layer comprising a first conductive material;

a first fill layer on a first portion of the liner layer and comprising a second conductive material; and

a second fill layer on a second portion of the liner layer and comprising a third conductive material.

7 . The semiconductor device of claim 6 , wherein a portion of the second fill layer extends in the via along part of the side of the source/drain region.

8 . The semiconductor device of claim 7 , wherein the portion of the second fill layer is bordered on two sides by the first fill layer and on one side by the liner layer.

9 . The semiconductor device of claim 6 , wherein the first fill layer occupies a majority of the via.

10 . The semiconductor device of claim 6 , wherein the first conductive material comprises one of tantalum, tantalum nitride and titanium nitride, the second conductive material comprises a noble metal and the third conductive material comprises one of cobalt, copper and tungsten.

11 . An integrated circuit comprising:

a transistor comprising a source/drain region;

a contact disposed on the source/drain region;

a power element;

an isolation region disposed on the power element; and

a via extending from the contact through the isolation region to the power element;

wherein the contact and the via each comprise a plurality of conductive materials; and

wherein the via comprises:

a liner layer comprising a first conductive material;

a first fill layer on a first portion of the liner layer and comprising a second conductive material; and

a second fill layer on a second portion of the liner layer and comprising a third conductive material.

12 . The integrated circuit of claim 11 , wherein the power element comprises a power rail.

13 . The integrated circuit of claim 11 , wherein at least a portion of the via is disposed along a side of the source/drain region.

14 . The integrated circuit of claim 11 , wherein a portion of the second fill layer extends in the via along part of a side of the source/drain region, and wherein the portion of the second fill layer is bordered on two sides by the first fill layer and on one side by the liner layer.

15 . A semiconductor device, comprising:

a source/drain region disposed on a first side of a semiconductor layer;

a contact disposed on the source/drain region on the first side of the semiconductor layer;

a power element disposed on a second side of the semiconductor layer; and

a via extending from the contact along a side of the source/drain region to the power element;

wherein the contact and the via each comprise a plurality of conductive materials; and

wherein the via comprises:

a liner layer comprising a first conductive material;

a first fill layer on a first portion of the liner layer and comprising a second conductive material; and

a second fill layer on a second portion of the liner layer and comprising a third conductive material.

16 . The semiconductor device of claim 15 , wherein the power element comprises a power rail.

17 . The semiconductor device of claim 15 , further comprising an isolation region disposed on a side of the semiconductor layer, wherein the via extends through the isolation region to contact the power element.