Backside BPR/BSPDN integration with backside local interconnect
A semiconductor device includes backside power rails located between N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor space; and backside local signal lines located between the backside power rails.
1 . A semiconductor device comprising:
backside power rails located between at least one N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor spaces; and
backside local signal lines located between the backside power rails, wherein the backside local signal lines connect to at least one source/drain or at least one gate through at least one backside contact.
2 . The semiconductor device of claim 1 , wherein the backside power rails connect to source/drain epitaxies through respective backside contacts.
3 . The semiconductor device of claim 1 , further comprising a cell architecture with the backside local signal lines running horizontally on a backside, and a frontside metal running vertically.
4 . The semiconductor device of claim 1 , further comprising at least one pair of adjacent N channel transistors.
5 . The semiconductor device of claim 4 , wherein the backside power rails comprise at least one backside N channel power rail for the at least one pair of adjacent N channel transistors, the at least one backside N channel power rail located between the at least one pair of adjacent N channel transistors.
6 . The semiconductor device of claim 4 , further comprising two adjacent P channel transistors, wherein at least one N channel transistor of the at least one pair of adjacent N channel transistors is adjacent to a P channel transistor of the two adjacent P channel transistors.
7 . The semiconductor device of claim 6 , further comprising at least one backside P channel power rail for the two adjacent P channel transistors, the at least one backside P channel power rail located between the two adjacent P channel transistors.
8 . The semiconductor device of claim 6 , further comprising backside local signal lines for the N channel field effect transistors and the P channel field effect transistors, the backside local signal lines located between at least one of the N channel field effect transistors and at least one of the P channel field effect transistors.
9 . A semiconductor device comprising:
two adjacent N channel transistors; and
two adjacent P channel transistors, wherein a N channel transistor of the two adjacent N channel transistors is adjacent to a P channel transistor of the two adjacent P channel transistors;
wherein backside N channel power rails for the two adjacent N channel transistors are located between the two adjacent N channel transistors and wherein backside P channel power rails for the two adjacent P channel transistors are located between the two adjacent P channel transistors and wherein backside local signal lines for the N channel transistors and P channel transistors are located between the adjacent N channel transistor and P channel transistor.
10 . The semiconductor device of claim 9 , further comprising at least one backside contact to connect to at least one source/drain or at least one gate.
11 . The semiconductor device of claim 10 , wherein the backside N channel power rails connect to the at least one source/drain with the at least one backside contact.
12 . The semiconductor device of claim 10 , wherein the backside local signal lines connect to the at least one source/drain or the at least one gate with the at least one backside contact.
13 . The semiconductor device of claim 9 , further comprising a cell architecture with the backside local signal lines running horizontally on a backside, and a frontside metal running vertically.