Integrated circuit semiconductor device

1 . An integrated circuit semiconductor device, comprising:

a substrate having a first surface and a second surface opposite to the first surface;

a power via penetrating between the first surface and the second surface of the substrate;

a cell part including a plurality of individual elements having different thicknesses inside the substrate; and a recess between the individual elements;

a signal wiring part on the first surface of the substrate and including an upper multilayer wiring layer connected to the power via;

a power transmission network part under the second surface of the substrate and including a lower multilayer wiring layer connected to the power via; and

an external connection terminal under the power transmission network part and connected to the lower multilayer wiring layer,

wherein the substrate includes a plurality of regions having different thicknesses.

2 . The integrated circuit semiconductor device as claimed in claim 1 , wherein:

the substrate includes a first region in which a first individual element of the cell part is positioned and a second region in which a second individual element of the cell part is positioned, and

a dopant depth of the second individual element is greater than a dopant depth of the first individual element.

3 . The integrated circuit semiconductor device as claimed in claim 2 , wherein:

the cell part includes a first recess positioned in the first region and a second recess positioned in the second region,

the first region of the substrate has a first thickness from a lower surface of the first recess to the second surface of the substrate and the second region of the substrate has a second thickness from a lower surface of the second recess to the second surface of the substrate, and

the second thickness of the second region is greater than the first thickness of the first region.

4 . The integrated circuit semiconductor device as claimed in claim 3 , wherein:

the first thickness of the first region is from about 100 nm to about 350 nm, and

the second thickness of the second region is at least about 100 nm greater than the first thickness of the first region.

5 . The integrated circuit semiconductor device as claimed in claim 1 , wherein:

the cell part further includes a nanosheet, a local interconnect, and a cell via,

the nanosheet connects the individual elements to the local interconnect, and

the cell via connects the local interconnect to the upper multilayer wiring layer of the signal wiring part.

6 . The integrated circuit semiconductor device as claimed in claim 1 , wherein:

the cell part includes a horizontal transistor and a vertical transistor,

the substrate includes a first region in which the horizontal transistor of the cell part is positioned and a second region in which the vertical transistor of the cell part is positioned,

the cell part includes a first recess in the first region and a second recess in the second region,

the first region of the substrate has a first thickness from a lower surface of the first recess to the second surface of the substrate, and the second region of the substrate has a second thickness from a lower surface of the second recess to the second surface of the substrate, and

the second thickness of the second region is greater than the first thickness of the first region.

7 . The integrated circuit semiconductor device as claimed in claim 6 , wherein:

the first thickness of the first region is from about 100 nm to about 350 nm,

the second thickness of the second region is at least about 100 nm greater than the first thickness of the first region.

8 . The integrated circuit semiconductor device as claimed in claim 1 , wherein the cell part includes a plurality of memory devices having different thicknesses.

9 . The integrated circuit semiconductor device as claimed in claim 8 , wherein:

the plurality of memory devices includes a first memory device and a second memory device,

a thickness of the second memory device of the cell part is greater than a thickness of the first memory device of the cell part,

the substrate includes a first region in which the first memory device of the cell part is positioned and a second region in which the second memory device of the cell part is positioned,

the cell part includes a first recess positioned in the first region and a second recess positioned in the second region,

the first region of the substrate has a first thickness from a lower surface of the first recess to the second surface of the substrate and the second region of the substrate has a second thickness from a lower surface of the second recess to the second surface of the substrate, and

the second thickness of the second region is greater than the first thickness of the first region.

10 . The integrated circuit semiconductor device as claimed in claim 1 , wherein:

the cell part includes a buried conductive line and a protruding conductive line, and

the power via is connected to at least one of the buried conductive line and the protruding conductive line of the cell part.

11 . The integrated circuit semiconductor device as claimed in claim 1 ,

wherein the power via is one of a plurality of power vias penetrating between the first surface and the second surface, and

wherein the plurality of power vias have different horizontal widths.

12 . The integrated circuit semiconductor device as claimed in claim 11 , wherein:

the substrate includes a first region in which a first individual element of the cell part is positioned and a second region in which a second individual element of the cell part is positioned,

a thickness of the second individual element is greater than a thickness of the first individual element,

the plurality of power vias comprise a first power via having a first width and a second power via having a second width, and

the first power via passes through the first region of the substrate, and the second power via passes through the second region of the substrate.

13 . The integrated circuit semiconductor device as claimed in claim 12 , wherein the second width of the second power via is greater than the first width of the first power via.

14 . The integrated circuit semiconductor device as claimed in claim 13 , wherein:

the first width of the first power via is about 50 nm to about 100 nm, and

the second width of the second power via is about 200 nm to about 700 nm.

15 . The integrated circuit semiconductor device as claimed in claim 12 , wherein:

the cell part includes a first recess positioned in the first region and a second recess positioned in the second region,

the first region of the substrate has a first thickness from a lower surface of the first recess to the second surface of the substrate

the second region of the substrate has a second thickness from a lower surface of the second recess to the second surface of the substrate, and

the second thickness of the second region is greater than the first thickness of the first region.

16 . The integrated circuit semiconductor device as claimed in claim 15 , wherein:

the first thickness of the first region of the substrate is from about 100 nm to about 350 nm, and

the second thickness of the second region of the substrate is at least about 100 nm greater than the first thickness of the first region.

17 . The integrated circuit semiconductor device as claimed in claim 11 , wherein:

the cell part includes a horizontal transistor and a vertical transistor,

the substrate includes a first region in which the horizontal transistor of the cell part is positioned and a second region in which the vertical transistor of the cell part is positioned,

the plurality of power vias comprise a first power via having a first width and a second power via having a second width,

the second width of the second power via is greater than the first width of the first power via, and

the first power via passes through the first region of the substrate, and the second power via passes through the second region of the substrate.

18 . The integrated circuit semiconductor device as claimed in claim 11 , wherein:

the cell part includes a plurality of memory devices,

the plurality of memory devices include a first memory device and a second memory device,

a thickness of the second memory device of the cell part is greater than a thickness of the first memory device of the cell part,

the substrate includes a first region in which the first memory device of the cell part is positioned and a second region in which the second memory device of the cell part is positioned,

the plurality of power vias include a first power via having a first width and a second power via having a second width,

the second width of the second power via is greater than the first width of the first power via, and

the first power via passes through the first region of the substrate, and the second power via passes through the second region of the substrate.

19 . The integrated circuit semiconductor device as claimed in claim 11 , wherein the plurality of power vias have a shape in which a horizontal width thereof narrows toward the first surface of the substrate.

20 . The integrated circuit semiconductor device as claimed in claim 1 ,

wherein the substrate includes a first region in which a first individual element of the cell part is positioned and a second region in which a second individual element of the cell part is positioned,

wherein a thickness of the second individual element of the cell part is greater than a thickness of the first individual element of the cell part,

wherein the cell part includes a first recess positioned in the first region and a second recess positioned in the second region,

wherein the first region of the substrate has a first thickness from a lower surface of the first recess to the second surface of the substrate,

wherein the second region of the substrate has a second thickness from a lower surface of the second recess to the second surface of the substrate,

wherein the first thickness of the first region of the substrate is from about 100 nm to about 350 nm, and the second thickness of the second region of the substrate is at least about 100 nm greater than the first thickness,

wherein the power via is one of a plurality of power vias that include a first power via having a first width and a second power via having a second width, and the first power via passes through the first region of the substrate and the second power via passes through the second region of the substrate, and

wherein the first width of the first power via is about 50 nm to about 100 nm, and the second width of the second power via is about 200 nm to about 700 nm.