IP Library Granted Patent US 12696752
Granted Patent B2
US 12696752 · App. 18/577,304 · Granted Jul 28, 2026

Semiconductor device and method for manufacturing the same

Inventor: Koichiro Nishizawa (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H10W20/425H10W20/035H10W20/0526
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12696752
App. No.
18/577,304
Granted
Jul 28, 2026
Kind
B2
Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same, and an object thereof is to provide a semiconductor and a method for manufacturing the same, the semiconductor device not diffusing a material of a metal layer to a semiconductor substrate. A semiconductor device of the present disclosure includes a semiconductor substrate which is formed of GaAs, a first barrier layer which is formed of an alloy containing Ni on the semiconductor substrate, a second barrier layer which is formed of Co or an alloy containing Co on the first barrier layer, and a metal layer which is formed on the second barrier layer. A Ni concentration in the first barrier layer is 80 at % or lower.

Claims (26)

1 . A semiconductor device comprising:

a semiconductor substrate which is formed of GaAs;

a first barrier layer which is formed of an alloy containing Ni on the semiconductor substrate;

a second barrier layer which is formed of Co or an alloy containing Co on the first barrier layer; and

a metal layer which is formed on the second barrier layer, wherein

a Ni concentration in the first barrier layer is 80 at % or lower.

2 . The semiconductor device according to claim 1 , comprising

a diffusion prevention layer which contains metal exhibiting catalytic activity

between the first barrier layer and the second barrier layer.

3 . The semiconductor device according to claim 2 , comprising

a deposition layer in which metal exhibiting catalytic activity is deposited

between the semiconductor substrate and the first barrier layer.

4 . The semiconductor device according to claim 1 , comprising

a deposition layer in which metal exhibiting catalytic activity is deposited

between the semiconductor substrate and the first barrier layer.

5 . A method of manufacturing a semiconductor device, the method comprising:

a step of forming a deposition layer, in which metal exhibiting catalytic activity is deposited, on a semiconductor substrate formed of GaAs;

a step of forming a first barrier layer, which is formed of an alloy containing Ni, on the deposition layer by a plating method;

a step of forming a second barrier layer, which is formed of Co or an alloy containing Co, on the first barrier layer by the plating method;

a step of forming a metal layer on the second barrier layer; and

a step of conducting a heat treatment until a Ni concentration in the first barrier layer becomes 80 at % or lower.

6 . The method of manufacturing a semiconductor device according to claim 4 , the method comprising

a step of forming a diffusion prevention layer, which contains metal exhibiting catalytic activity,

between the first barrier layer and the second barrier layer.

7 . The method of manufacturing a semiconductor device according to claim 6 , wherein

the diffusion prevention layer is formed by an evaporation method or a sputtering method.