Semiconductor device
A semiconductor device includes a semiconductor chip including a substrate, a transistor provided on an upper surface of the substrate and having an input electrode to which a high frequency signal is input, an output electrode from which the high frequency signal is output, and a reference potential electrode to which a reference potential is supplied, and a metal pattern provided on the upper surface of the substrate and electrically connected to the reference potential electrode, a first capacitor including a first lower electrode provided on the metal pattern and electrically connected to the metal pattern, a first dielectric layer provided on the first lower electrode, and a first upper electrode provided on the first dielectric layer, and a first bonding wire electrically connecting the first upper electrode and a first electrode which is any one of the input electrode and the output electrode.
1 . A semiconductor device comprising:
a semiconductor chip including:
a substrate;
a transistor provided on an upper surface of the substrate and having an input electrode to which a high frequency signal is input, an output electrode from which the high frequency signal is output, and a reference potential electrode to which a reference potential is supplied; and
a metal pattern provided on the upper surface of the substrate and electrically connected to the reference potential electrode;
a first capacitor including:
a first lower electrode provided on the metal pattern and electrically connected to the metal pattern,
a first dielectric layer provided on the first lower electrode, and
a first upper electrode provided on the first dielectric layer;
a first bonding wire electrically connecting the first upper electrode and a first electrode which is any one of the input electrode and the output electrode;
a conductive base on which the semiconductor chip is mounted and to which the reference potential is supplied;
a second capacitor provided on a region of the base other than another region where the semiconductor chip is mounted and including a second lower electrode electrically connected to the conductive base, a second dielectric layer provided on the second lower electrode, and a second upper electrode provided on the second dielectric layer; and
a second bonding wire electrically connecting the second upper electrode and a second electrode other than the first electrode of the input electrode and the output electrode.
2 . The semiconductor device according to claim 1 , wherein
the first lower electrode is connected on the metal pattern by using a brazing filler metal.
3 . The semiconductor device according to claim 1 , wherein
the first dielectric layer is a ceramic substrate or a semiconductor substrate.
4 . The semiconductor device according to claim 1 , wherein
the first lower electrode is in contact with the metal pattern, and the first dielectric layer is provided from a region of an upper surface of the metal pattern where the first lower electrode is not provided to another region between the first lower electrode and the first upper electrode.
5 . The semiconductor device according to claim 1 , further comprising:
a first signal terminal; and
a third bonding wire electrically connecting the first upper electrode and the first signal terminal.
6 . The semiconductor device according to claim 1 , further comprising:
a second signal terminal; and
a fourth bonding wire electrically connecting the second upper electrode and the second signal terminal.
7 . The semiconductor device according to claim 1 , wherein
the first electrode is the input electrode, and the second bonding wire is longer than the first bonding wire.
8 . The semiconductor device according to claim 1 , further comprising:
wherein the metal pattern and the reference potential electrode are electrically connected to the conductive base via a via hole penetrating through the substrate.