Semiconductor package
Disclosed is a semiconductor package comprising a solder ball, a printed circuit board on the solder ball, a bump on the printed circuit board, and a semiconductor chip on the bump. The printed circuit board includes a base substrate, a low-k dielectric layer that penetrates the base substrate, a connection conductive structure electrically connected to the bump and surrounded by the low-k dielectric layer, and a lower conductive structure electrically connected to the solder ball and the connection conductive structure. A top surface of the lower conductive structure is in contact with a first bottom surface of the low-k dielectric layer.
1 . A semiconductor package, comprising:
a solder ball;
a printed circuit board on the solder ball;
a bump on the printed circuit board; and
a semiconductor chip on the bump,
wherein the printed circuit board includes:
a base substrate;
a low-k dielectric layer that penetrates the base substrate from an upper surface of the base substrate to a lower surface of the base substrate;
a connection conductive structure electrically connected to the bump and surrounded by the low-k dielectric layer; and
a lower conductive structure electrically connected to the solder ball and the connection conductive structure,
wherein a top surface of the lower conductive structure is in contact with a first bottom surface of the low-k dielectric layer.
2 . The semiconductor package of claim 1 , wherein a dielectric constant of the low-k dielectric layer is less than a dielectric constant of the base substrate.
3 . The semiconductor package of claim 1 , wherein
the printed circuit board further includes a lower solder resist layer that covers a bottom surface of the base substrate, and
the lower conductive structure is between top and bottom surfaces of the lower solder resist layer.
4 . The semiconductor package of claim 1 , wherein the connection conductive structure includes:
a connection conductive pad electrically connected to the bump; and
a connection conductive via electrically connected to the connection conductive pad.
5 . The semiconductor package of claim 4 , wherein an entirety of the connection conductive via vertically overlaps the bump.
6 . The semiconductor package of claim 5 , wherein a bottom surface of the connection conductive via is in contact with the top surface of the lower conductive structure.
7 . The semiconductor package of claim 1 , wherein
the low-k dielectric layer has a second bottom surface at a level lower than a level of the first bottom surface of the low-k dielectric layer, and
a bottom surface of the lower conductive structure is coplanar with the second bottom surface of the low-k dielectric layer.
8 . The semiconductor package of claim 1 , wherein the top surface of the lower conductive structure is in contact with a bottom surface of the connection conductive structure.
9 . The semiconductor package of claim 1 , wherein a dielectric constant of the low-k dielectric layer is in a range of about 1.2 to about 3.2.
10 . A semiconductor package, comprising:
a solder ball;
a printed circuit board on the solder ball;
a bump on the printed circuit board; and
a semiconductor chip on the bump,
wherein the printed circuit board includes:
a low-k dielectric layer;
a base substrate that surrounds the low-k dielectric layer;
a connection conductive structure that is electrically connected to the bump and penetrates the low-k dielectric layer in a vertical direction; and
a lower conductive structure electrically connected to the solder ball and the connection conductive structure,
wherein the lower conductive structure is at a level lower than a level of the base substrate.
11 . The semiconductor package of claim 10 , wherein a dielectric constant of the low-k dielectric layer is less than a dielectric constant of the base substrate.
12 . The semiconductor package of claim 11 , wherein
the dielectric constant of the low-k dielectric layer is in a range of about 1.2 to about 3.2, and
the dielectric constant of the base substrate is in a range of about 3.5 to about 4.2.
13 . The semiconductor package of claim 10 , wherein the printed circuit board further includes:
an upper solder resist layer that covers a top surface of the base substrate; and
an upper conductive structure surrounded by the upper solder resist layer.
14 . The semiconductor package of claim 13 , wherein the printed circuit board further includes a solder overlap via electrically connected to the upper conductive structure,
wherein the solder overlap via penetrates the base substrate in the vertical direction.
15 . The semiconductor package of claim 14 , wherein the printed circuit board further includes:
a lower solder resist layer that covers a bottom surface of the base substrate; and
a solder overlap pad in the lower solder resist layer,
wherein the solder overlap pad is electrically connected to the solder overlap via.
16 . The semiconductor package of claim 10 , wherein
the connection conductive structure is one of a plurality of connection conductive structures included in the printed circuit board, and
the lower conductive structure is one of a plurality of lower conductive structures included in the printed circuit board.
17 . The semiconductor package of claim 10 , wherein the semiconductor chip includes a substrate and a first wiring structure that covers a bottom surface of the substrate,
wherein a distance between the first wiring structure and the lower conductive structure is greater than a thickness of the printed circuit board.
18 . The semiconductor package of claim 10 , wherein the printed circuit board further includes a lower solder resist layer that covers a bottom surface of the base substrate,
wherein the lower solder resist layer surrounds the lower conductive structure.
19 . A semiconductor package, comprising:
a solder ball;
a printed circuit board on the solder ball;
a bump on the printed circuit board;
a semiconductor chip on the bump; and
an adhesion layer between the semiconductor chip and the printed circuit board,
wherein the printed circuit board includes:
a base substrate;
an upper solder resist layer that covers a top surface of the base substrate;
a lower solder resist layer that covers a bottom surface of the base substrate;
a low-k dielectric layer that penetrates the base substrate;
a connection conductive structure electrically connected to the bump and surrounded by the low-k dielectric layer; and
a lower conductive structure electrically connected to the solder ball and the connection conductive structure,
wherein a top surface of the lower conductive structure is in contact with a first bottom surface of the low-k dielectric layer and a bottom surface of the connection conductive structure,
wherein the lower solder resist layer covers a second bottom surface of the low-k dielectric layer and a bottom surface of the lower conductive structure, and
wherein the second bottom surface of the low-k dielectric layer is at a level lower than a level of the first bottom surface of the low-k dielectric layer.