IP Library › Granted Patent US 12696776
Granted Patent B2
US 12696776 · App. 18/086,293 · Granted Jul 28, 2026

Glass substrate device with embedded components

Inventors: Bohan Shan (Chandler, AZ); Haobo Chen (Chandler, AZ); Yiqun Bai (Chandler, AZ); Dingying Xu (Chandler, AZ); Srinivas Venkata Ramanuja Pietambaram (Chandler, AZ); Hongxia Feng (Chandler, AZ); Gang Duan (Chandler, AZ); Xiaoying Guo (Chandler, AZ); Ziyin Lin (Chandler, AZ); Bai Nie (Chandler, AZ); Kyle Jordan Arrington (Gilbert, AZ); Jeremy D. Ecton (Gilbert, AZ); Brandon C. Marin (Gilbert, AZ)
Assignee: Intel Corporation
H10W70/614H10B80/00H10W70/611H10W70/65H10W90/00H10W90/701H10W72/242H10W72/923H10W72/952
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Quick Facts
Patent No.
US 12696776
App. No.
18/086,293
Granted
Jul 28, 2026
Kind
B2
Abstract

An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.

Claims (50)

1 . An electronic system, comprising:

a substrate comprising:

a glass core layer comprising multiple cavities formed through the glass core layer;

at least one glass core layer active component die in a cavity of the multiple cavities;

at least one discrete passive component in another cavity of the multiple cavities;

a mold layer comprising at least one mold layer active component die in the mold layer; and

a first buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer and comprising electrically conductive interconnects connecting the at least one glass core layer active component die, the at least one discrete passive component, and the at least one mold layer active component die; and

at least one top surface active component die attached to the top surface of the substrate and electrically connected to the at least one mold layer active component die.

2 . The electronic system of claim 1 , wherein the at least one glass core layer active component die is a high bandwidth memory (HBM) component, the at least one discrete passive component is a discrete inductor, the at least one mold layer active component die is an input/output (I/O) component die, and the at least one top surface active component die is a compute component die.

3 . The electronic system of claim 1 , comprising a second buildup layer contacting bottom surface of the glass core layer, wherein the at least one glass core layer active component die extends outside the glass core layer into the second buildup layer and the at least one discrete passive component contacts the top surface of the second buildup layer.

4 . The electronic system of claim 3 , wherein the second buildup layer comprises at least one via connected to the at least one discrete passive component and extending to a bottom surface of the substrate.

5 . The electronic system of claim 1 , comprising:

a second buildup layer contacting the bottom surface of the glass core layer; and

a third buildup layer contacting a top surface of the mold layer, wherein the third buildup layer comprises electrically conductive interconnects and the at least one top surface active component die is attached to the electrically conductive interconnects of the third buildup layer.

6 . The electronic system of claim 5 , comprising one or more copper pillars that extend from the first buildup layer through the mold layer and the third buildup layer to the top surface of the substrate, wherein the at least one top surface active component die is electrically connected to the one or more copper pillars.

7 . The electronic system of claim 1 , comprising at least one multi-die interconnect bridge in the first buildup layer and connecting the at least one discrete passive component and the at least one mold layer active component die.

8 . The electronic system of claim 7 , wherein the at least one discrete passive component is a discrete capacitor, and the at least one mold layer active component die is an input/output (I/O) component die.

9 . The electronic system of claim 7 , wherein the multi-die interconnect bridge comprises a bottom surface electrically connected to the at least one discrete passive component and a top surface electrically connected to the at least one mold layer active component die.

10 . The electronic system of claim 1 , wherein the glass core layer comprises multiple glass core layer active component dies and multiple discrete passive components in the multiple cavities, a bottom surface of the substrate comprises a bonding pad electrically connected to the at least one discrete passive component of the multiple discrete passive components, the mold layer comprises multiple mold layer active component dies, a height of the mold layer is a uniform height, and wherein at least one top surface active component die comprises multiple top surface active component dies electrically connected to the glass core layer active component dies and the mold layer active component dies.

11 . The electronic system of claim 10 , comprising at least one multi-die interconnect bridge electrically connected to at least two discrete passive components of the multiple discrete passive components and at least two mold layer component dies of the multiple mold layer active component dies.

12 . A method of making a substrate for an electronic system, comprising:

forming multiple cavities in a glass core layer of the substrate;

forming a first buildup layer of dielectric material on a first surface of the glass core layer;

disposing at least one glass core layer active component die in at least one cavity of the multiple cavities and disposing at least one discrete passive component in at least one other cavity of the cavities of the multiple cavities;

forming a layer of electrically conductive interconnects in the first buildup layer comprising die bonding pads;

disposing at least one mold layer active component die on the first buildup layer attached to at least a portion of the die bonding pads of the first buildup layer; and

disposing a mold material on the first buildup layer to encapsulate the at least one mold layer active component die.

13 . The method of claim 12 , comprising:

forming a second buildup layer of dielectric material on a second surface of the glass core layer; and

extending one or more of the multiple cavities of the glass core layer into at least one cavity portion of the second buildup layer, wherein the disposing the at least one glass core layer active component die and the at least one discrete passive component comprises disposing the at least one glass core layer active component die in the at least one cavity portion of the second buildup layer, and disposing the at least one discrete passive component on a surface of the second buildup layer.

14 . The method of claim 12 , comprising:

forming a third buildup layer on a surface of the mold material, wherein the third buildup layer comprises die bonding pads on a surface of the third buildup layer that is a top surface of the substrate.

15 . The method of claim 14 , comprising:

forming one or more copper pillars that extend from the first buildup layer through the mold material to the top surface of the third buildup layer; and

forming a die bonding pad of the third buildup layer on one or more of the copper pillars.

16 . The method of claim 12 , wherein the forming the layer of electrically conductive interconnects comprises:

disposing at least one multi-die interconnect bridge in the first buildup layer; and

electrically connecting the at least one discrete passive component to the at least one mold layer active component die using the multi-die interconnect bridge.

17 . The method of claim 12 , wherein the disposing the at least one glass core layer active component die and at least one discrete passive component comprises:

disposing a high bandwidth memory (HBM) component in the at least one cavity and disposing at least one discrete inductor in the at least one other cavity, wherein the disposing at least one mold layer active component die comprises disposing at least one input/output (I/O) component die on the first buildup layer.

18 . A substrate for an electronic system, the substrate comprising:

a glass core layer comprising multiple cavities in the glass core layer;

multiple high bandwidth memory (HBM) components, a high bandwidth memory component in each cavity of a first portion of the multiple cavities;

multiple discrete inductors, a discrete inductor in each cavity of a second portion of the multiple cavities;

multiple input/output (I/O) component dies arranged in a mold layer, the mold layer having a first surface facing a surface of the glass core layer;

a multi-die interconnect bridge connecting the multiple discrete inductors to the multiple I/O component dies; and

a first redistribution layer arranged on a second surface of the mold layer and comprising electrically conductive interconnects, the electrically conductive interconnects comprising multiple die bonding pads on a top surface of the first redistribution layer.

19 . The substrate of claim 18 , comprising multiple copper pillars that extend through the mold layer and the first redistribution layer, wherein at least one of the copper pillars contacts a die bonding pad on the top surface of the first redistribution layer.

20 . The substrate of claim 19 , comprising:

a second redistribution layer arranged between the glass core layer and the mold layer and comprising electrically conductive interconnects, wherein the electrically conductive interconnects of the second redistribution layer provides electrical continuity between the multiple HBM components and the copper pillars, and the copper pillars provide electrical continuity from the electrically conductive interconnects of the second redistribution layer to one or more of the multiple die bonding pads on the top surface of the first redistribution layer.