IP Library › Granted Patent US 12696778

Granted Patent B2

US 12696778 · App. 17/853,205 · Granted Jul 28, 2026

Semiconductor package including connecting pads

Inventors: Yae Jung Yoon (Hwaseong-si, KR); Eung Kyu Kim (Yongin-si, KR); Min Jun Bae (Hwaseong-si, KR); Kyoung Lim Suk (Suwon-si, KR); Seok Hyun Lee (Hwaseong-si, KR); Jae Gwon Jang (Hwaseong-si, KR)

Assignee: Samsung Electronics Co., Ltd.

H10W70/65 H10W70/685 H10W74/131 H10W76/15 H10W90/00 H10W90/701 H10W72/072 H10W72/252 H10W72/952 H10W74/15 H10W90/724 H10W90/734

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Quick Facts

Patent No.: US 12696778
App. No.: 17/853,205
Granted: Jul 28, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor package including a passivation film, a mold layer on the passivation film, a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion, the first portion penetrating the passivation film, the second portion penetrating a part of the mold layer, a solder ball on the first portion of the connecting pad, an element on the second portion of the connecting pad, a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern inside the insulating layer, and a semiconductor chip on the wiring structure may be provided.

Claims (78)

1 . A semiconductor package comprising:

a passivation film;

a mold layer on the passivation film;

a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion, the first portion penetrating the passivation film, the second portion penetrating a part of the mold layer;

a solder ball on the first portion of the connecting pad;

an element in the mold layer and on the second portion of the connecting pad;

a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern inside the insulating layer;

an element pad in the mold layer and on the element, the element pad electrically connected to the element and the wiring pattern; and

a semiconductor chip on the wiring structure,

wherein the first portion of the connecting pad is in contact with the solder ball, wherein the second portion of the connecting pad is in contact with the element, and

wherein a width of the second portion of the connecting pad in a first direction parallel to an upper surface of the passivation film is greater than a width of the first portion of the connecting pad in the first direction.

2 . The semiconductor package of claim 1 , wherein a lower surface of the passivation film is on a same plane as a lower surface of the first portion of the connecting pad.

3 . The semiconductor package of claim 1 , wherein the solder ball is not inside the passivation film.

4 . The semiconductor package of claim 1 , wherein

the connecting pad includes a barrier film and a filling film on the barrier film, and

each of the first portion and the second portion includes the barrier film and the filling film.

5 . The semiconductor package of claim 4 , wherein the barrier film extends between the filling film and the passivation film, and does not extend between the filling film and the solder ball.

6 . The semiconductor package of claim 1 , further comprising:

a post penetrating the mold layer and electrically connecting the connecting pad and the wiring pattern.

7 . The semiconductor package of claim 1 , wherein at least a part of the element overlaps the semiconductor chip in a second direction perpendicular to the upper surface of the passivation film.

8 . The semiconductor package of claim 1 , wherein

the wiring pattern including a wiring layer and a wiring via on the wiring layer, and

a width of the wiring via in the first direction increases as being away from the mold layer.

9 . The semiconductor package of claim 8 , wherein the width of the first portion of the connecting pad in the first direction increases as being away from the solder ball.

10 . A semiconductor package comprising:

a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion;

a passivation film wrapping the first portion of the connecting pad;

a mold layer on the passivation film and wrapping the second portion of the connecting pad;

a wiring structure on the mold layer and including an insulating layer and a wiring pattern inside the insulating layer;

a post penetrating the mold layer and electrically connected to the second portion of the connecting pad and the wiring pattern;

an element in the mold layer and on the second portion of the connecting pad, the element including an element pad on an upper surface thereof, the element pad electrically connected to the wiring pattern; and

a solder ball on the first portion of the connecting pad,

wherein the first portion of the connecting pad is in contact with the solder ball,

wherein the second portion of the connecting pad is in contact with the element, and

11 . The semiconductor package of claim 10 , wherein

the wiring pattern including a wiring layer and a wiring via on the wiring layer,

a width of the wiring via in the first direction increases as being away from the mold layer, and

the width of the first portion of the connecting pad in the first direction increases as being away from the solder ball.

12 . The semiconductor package of claim 10 , wherein

the passivation film exposes a lower surface of the first portion of the connecting pad.

13 . The semiconductor package of claim 10 , further comprising:

an adhesive layer between the element and the passivation film.

14 . The semiconductor package of claim 13 , wherein the adhesive layer extends between the element and the connecting pad.

15 . The semiconductor package of claim 10 , wherein

the connecting pad includes a filling film and a barrier film between the filling film and the passivation film, and

each of the first portion and the second portion includes the barrier film and the filling film.

16 . A semiconductor package comprising:

a passivation film;

a first mold layer on the passivation film;

a first solder ball in contact with the first portion of the connecting pad;

an element on the second portion of the connecting pad;

an adhesive layer between the passivation film and the element;

an element pad in the first mold layer and on the element;

a first wiring structure on the first mold layer, the first wiring structure including a first insulating layer and a first wiring pattern inside the first insulating layer, the first wiring pattern electrically connected to the element pad;

a post penetrating the first mold layer and electrically connected to the first wiring pattern and the second portion of the connecting pad;

a first semiconductor chip on the first wiring structure and overlapping at least a part of the element;

a second solder ball between the first wiring structure and the first semiconductor chip; and

a second mold layer on the first wiring structure, the second mold layer covering the first wiring structure and the first semiconductor chip,

wherein the first portion of the connecting pad is in contact with the first solder ball,

wherein the second portion of the connecting pad is in contact with the element, and

17 . The semiconductor package of claim 16 , wherein

the first wiring pattern including a first wiring layer and a first wiring via on the first wiring layer,

a width of the first wiring via in the first direction increases as being away from the first mold layer, and

the width of the first portion of the connecting pad in the first direction increases as being away from the first solder ball.

18 . The semiconductor package of claim 16 , further comprising:

a second semiconductor chip spaced apart from the first semiconductor chip and on the first wiring structure, the second semiconductor chip being different from the first semiconductor chip; and

a third solder ball between the first wiring structure and the second semiconductor chip.

19 . The semiconductor package of claim 16 , further comprising:

a through via on the first wiring structure, the through via penetrating the second mold layer and electrically connected to the first wiring pattern;

a second wiring structure on the second mold layer, the second wiring structure including a second insulating layer and a second wiring pattern, the second wiring pattern electrically connected to the through via; and

a second semiconductor chip on the second wiring structure and electrically connected to the second wiring pattern.

20 . The semiconductor package of claim 16 , further comprising:

a frame on the first wiring structure and penetrating the second mold layer, the frame including a frame insulating layer and a frame wiring pattern inside the frame insulating layer, the frame wiring pattern electrically connected to the first wiring pattern;

a second semiconductor chip on the second wiring structure and electrically connected to the second wiring pattern.