Packaging structure and packaging method
This disclosure relates to a packaging structure and a packaging method. The packaging structure includes: a substrate; an interconnecting structure, bonded to the substrate, the interconnecting structure is electrically connected to the substrate; a chipset, including a plurality of first chips stacked along a longitudinal direction, the first chip adjacent to the interconnecting structure is used as a bottom chip, each of the rest of the first chips is used as a top chip, the bottom chip is electrically connected to the interconnecting structure, adjacent first chips along the longitudinal direction are electrically connected, and a portion of the bottom chip is exposed from the top chip; a conductive post, arranged on the interconnecting structure on a side of the chipset and electrically connected to the interconnecting structure; and a second chip, bonded to the bottom chip exposed from the top chip and to the conductive post.
1 . A packaging structure, comprising:
a substrate;
an interconnecting structure, bonded to the substrate, wherein the interconnecting structure is electrically connected to the substrate;
a chipset, comprising a plurality of first chips stacked along a longitudinal direction, wherein a first chip of the plurality of first chips that is adjacent to the interconnecting structure is used as a bottom chip, each of the rest of the first chips is used as a top chip, the bottom chip is electrically connected to the interconnecting structure, adjacent first chips along the longitudinal direction are electrically connected, and a portion of the bottom chip is exposed from the top chip;
a conductive post, arranged on the interconnecting structure on a side of the chipset and electrically connected to the interconnecting structure; and
a second chip, directly stacked on and bonded to the bottom chip exposed from the top chip and to the conductive post, the second chip is electrically connected to the bottom chip and the conductive post;
wherein a top surface of the bottom chip and a top surface of the conductive post are substantially coplanar.
2 . The packaging structure according to claim 1 , wherein the interconnecting structure is a redistribution structure, and the redistribution structure comprises at least one redistribution layer.
3 . The packaging structure according to claim 1 , further comprising first conductive bumps arranged between the interconnecting structure and the bottom chip.
4 . The packaging structure according to claim 1 , wherein:
a partial region on the bottom chip exposed from the top chip is a first connection region;
the second chip comprises a first surface, the first surface comprises a second connection region and a third connection region, the second connection region is arranged opposite to the first connection region, and the third connection region is arranged opposite to the conductive post; and
the packaging structure further comprises second conductive bumps arranged between the second connection region and the first connection region and between the third connection region and the conductive post.
5 . The packaging structure according to claim 4 , further comprising a first sealing layer filling a gap between the bottom chip and the interconnecting structure, between the third connection region and the interconnecting structure, and between the second connection region and the first connection region, to seal the conductive post and the second conductive bumps.
6 . The packaging structure according to claim 1 , further comprising third conductive bumps arranged between the interconnecting structure and the substrate.
7 . The packaging structure according to claim 6 , further comprising a second sealing layer filling a gap between adjacent third conductive bumps between the interconnecting structure and the substrate.
8 . The packaging structure according to claim 1 , further comprising fourth conductive bumps arranged on a surface on a side of the substrate facing away from the interconnecting structure.
9 . The packaging structure according to claim 1 , further comprising a first packaging layer arranged on the bottom chip exposed from the second chip and covering a sidewall of the top chip.
10 . The packaging structure according to claim 1 , further comprising a second packaging layer arranged on the chipset and on the interconnecting structure on a side of the second chip.
11 . The packaging structure according to claim 1 , wherein a top surface of the conductive post is flush with a top surface of the bottom chip.
12 . The packaging structure according to claim 1 , wherein a partial region on the bottom chip exposed from the top chip is a first connection region, and a ratio of an area of the first connection region to a total area of the bottom chip ranges from 5% to 20%.
13 . The packaging structure according to claim 1 , wherein the bottom chip is a first logic chip, the top chip is a memory chip, and the second chip is a second logic chip.
14 . The packaging structure according to claim 1 , further comprising:
a thermally conductive layer, arranged on the chipset and the second chip; and
a packaging housing, arranged on the substrate, configured to package the chipset and the second chip, and in contact with the thermally conductive layer.