IP Library Granted Patent US 12696780
Granted Patent B2
US 12696780 · App. 18/532,864 · Granted Jul 28, 2026

Package comprising a substrate with cavity and an integrated device with a step back side

Inventors: Joan Rey Villarba Buot (Escondido, CA); Aniket Patil (San Diego, CA); Zhijie Wang (San Diego, CA)
Assignee: QUALCOMM INCORPORATED
H10W70/682H10W70/611H10W70/65H10W70/685H10W74/01H10W74/117H10W90/701H10W74/15H10W90/724H10W90/732H10W90/734
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12696780
App. No.
18/532,864
Granted
Jul 28, 2026
Kind
B2
Abstract

A package comprising a first substrate; an integrated device coupled to the first substrate, wherein the integrated device comprises a step back side; a second substrate comprising a cavity, wherein the integrated device is located at least partially in the cavity of the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer is located at least partially in the cavity of the second substrate.

Claims (41)

1 . A package comprising:

a first substrate;

an integrated device coupled to the first substrate, wherein the integrated device comprises a step back side, and the integrated device is coupled to the first substrate through at least a plurality of solder interconnects and a plurality of pillar interconnects;

a second substrate comprising a cavity, wherein the integrated device is located at least partially in the cavity of the second substrate; and

an encapsulation layer coupled to the first substrate and the second substrate,

wherein the encapsulation layer is located between the first substrate and the second substrate, and

wherein the encapsulation layer is located at least partially in the cavity of the second substrate.

2 . The package of claim 1 , wherein the integrated device comprises a die substrate that includes a step contour.

3 . The package of claim 2 , wherein the die substrate comprises a first thickness and a second thickness that is different from the first thickness.

4 . The package of claim 2 ,

wherein a first portion of the die substrate comprises a first width, and

wherein a second portion of the die substrate comprises a second width that is different from the first width.

5 . The package of claim 2 , further comprising a second die substrate coupled to the die substrate through an adhesive.

6 . The package of claim 1 , further comprising a plurality of ball interconnects and a plurality of solder interconnects coupled to the first substrate and the second substrate, wherein the plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate.

7 . The package of claim 6 , wherein the plurality of ball interconnects include copper core balls (CCBs).

8 . The package of claim 1 , wherein the cavity has a cavity width that is less than a width of the integrated device.

9 . The package of claim 1 ,

wherein the first substrate comprises:

at least one first dielectric layer; and

a first plurality of interconnects, and

wherein the second substrate comprises:

at least one second dielectric layer; and

a second plurality of interconnects.

10 . The package of claim 9 , wherein the second plurality of interconnects of the second substrate comprise a plurality of trace interconnects that are located laterally to the integrated device.

11 . The package of claim 9 , wherein the second plurality of interconnects of the second substrate comprise a plurality of trace interconnects that are (i) located laterally to the integrated device and (ii) vertically overlap with a portion of the integrated device.

12 . The package of claim 1 , further comprising a second integrated device coupled to the second substrate through at least a plurality of solder interconnects.

13 . The package of claim 1 , wherein the integrated device is coupled to the first substrate through at least one a plurality of solder interconnects.

14 . A method for fabricating a package, comprising:

providing a first substrate;

coupling an integrated device to the first substrate, wherein the integrated device comprises a step back side;

providing a second substrate comprising a cavity, wherein the second substrate is provided such that the integrated device is located at least partially in the cavity of the second substrate; and

forming an encapsulation layer that is coupled to the first substrate and the second substrate,

wherein the encapsulation layer is located between the first substrate and the second substrate,

wherein the encapsulation layer is located at least partially in the cavity of the second substrate, and

wherein the second substrate is coupled to the first substrate through a plurality of ball interconnects and a plurality of solder interconnects, and the plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate.

15 . The method of claim 14 , wherein the integrated device comprises a die substrate that includes a step contour.

16 . The method of claim 15 , wherein the die substrate comprises a first thickness and a second thickness that is different from the first thickness.

17 . The method of claim 15 ,

wherein a first portion of the die substrate comprises a first width, and

wherein a second portion of the die substrate comprises a second width that is different from the first width.

18 . The method of claim 15 , further comprising a second die substrate coupled to the die substrate.