Electrical traces on glass cores in integrated circuit packages and methods of manufacturing the same
Methods, apparatus, systems, and articles of manufacture are disclosed to enable electrical traces on glass cores in integrated circuit packages that includes an integrated circuit (IC) package substrate comprising a glass core, a photo-imageable dielectric (PID) material on the glass core, and metal interconnects in openings in the PID material.
1 . An integrated circuit (IC) package substrate comprising:
a glass core defined by a sheet of glass;
a photo-imageable dielectric (PID) material on the glass core; and
metal interconnects in openings in the PID material, the metal interconnects including electrical routing extending along a surface of the glass core, the electrical routing in direct contact with the glass.
2 . The IC package substrate of claim 1 , wherein the PID material includes at least one of polyimide (PI), polybenz-oxazoles (PBO), Benzocyclobutene (BCB), epoxy or an acrylic.
3 . The IC package substrate of claim 1 , wherein the metal interconnects include a through-glass-via (TGV) that extends through the glass core.
4 . The IC package substrate of claim 3 , wherein the metal interconnects include a contact pad at an end of the TGV, a width of the contact pad being larger than a width of the TGV.
5 . The IC package substrate of claim 1 , including a build-up layer dielectric material on the PID material, the build-up layer dielectric material different than the PID material.
6 . The IC package of claim 1 , wherein the PID material and the electrical routing have a same thickness.
7 . The IC package of claim 1 , wherein the PID material has a first surface facing away from glass core, and the metal interconnects have second surfaces facing away from glass core, the first surface coplanar with the second surfaces.
8 . An integrated circuit (IC) package comprising:
a semiconductor die; and
a package substrate to support the semiconductor die, the package substrate including:
a glass core;
a dielectric build-up layer having a first surface and a second surface, the first surface facing towards the glass core, the second surface facing away from the glass core; and
metal traces extending along a surface of the glass core, the metal traces closer to the glass core than the dielectric build-up layer is to the glass core, the first surface of the dielectric build-up layer in contact with the metal traces, the dielectric build-up layer not between the glass core and the metal traces.
9 . The IC package of claim 8 , including a photo-imageable dielectric (PID) material extending along the surface of the glass core, the metal traces within openings in the PID material.
10 . The IC package of claim 9 , wherein the PID material is at least one of polyimide (PI), polybenz-oxazoles (PBO), or Benzocyclobutene (BCB).
11 . The IC package of claim 9 , wherein the dielectric build-up layer is different than the PID material.
12 . The IC package of claim 9 , including at least one of an adhesion layer or a metal seed layer on the glass core, the at least one of the adhesion layer or the metal seed layer being the only material between the metal traces and the surface of the glass core.
13 . The IC package of claim 8 , wherein the metal traces are first metal traces, the IC package including second metal traces, the second metal traces in contact with the second surface of the dielectric build-up layer, the dielectric build-up layer closer to the glass core than the second metal traces are to the glass core.
14 . The IC package of claim 13 , wherein the first metal traces are in a first conductive layer, and the second metal traces are in a second conductive layer, and there are no other conductive layers defining other metal traces between the first and second conductive layers.
15 . The IC package of claim 9 , wherein the PID material includes a first surface proximate to the glass core and a second surface distal from the glass core, and the metal traces include third surfaces proximate to the glass core and fourth surfaces distal from the glass core, the first surface of the PID material aligned with the third surfaces of the metal traces, the second surface of the PID material aligned with the fourth surfaces of the metal traces.
16 . An integrated circuit (IC) package substrate comprising:
a glass core defined by a piece of glass;
a photo-imageable dielectric (PID) material on the glass core; and
metal interconnects in openings in the PID material, the metal interconnects including electrical routing extending along a surface of the glass core, the electrical routing not separated from the glass by any material other than at least one of an adhesion layer or a metal seed layer.
17 . The IC package substrate of claim 16 , wherein the adhesion layer has a first thickness and the PID material has a second thickness, the second thickness multiple times greater than the first thickness.
18 . The IC package substrate of claim 17 , wherein the first thickness is less than 500 nanometers.
19 . The IC package substrate of claim 16 , including the adhesion layer, the adhesion layer including at least one of silicon or nitride.
20 . The IC package substrate of claim 16 , including the metal seed layer, the metal seed layer including titanium.