Semiconductor package
A semiconductor package includes a package substrate, an encapsulated semiconductor device, and a plurality of conductive bumps. The package substrate includes a device mounting region, a plurality of substrate pads and a solder resist layer. The encapsulated semiconductor device is disposed over the device mounting region and includes a plurality of device pads. The conductive bumps are connected between the plurality of substrate pads and the plurality of device pads through the solder resist layer and includes a first conductive bump on a periphery of the device mounting region. A first contact area of the first conductive bump for contacting respective one of the substrate pads is substantially greater than a second contact area of the first conductive bump for contacting respective one of the device pads.
1 . A semiconductor package, comprising:
a package substrate comprising a plurality of substrate pads and a solder resist layer comprising an array of a plurality of second solder resist opening patterns and a plurality of first solder resist opening patterns surrounding the array of the plurality of second solder resist opening patterns, wherein diameters of the plurality of substrate pads disposed on an outermost surface of the package substrate are same, and a diameter of each of the plurality of first solder resist opening patterns is greater than a diameter of each of the plurality of second solder resist opening patterns;
an encapsulated semiconductor device over the package substrate and comprising a plurality of device pads, wherein a peripheral portion of the encapsulated semiconductor device is vertically closer to the package substrate than a center portion of the encapsulated semiconductor device is; and
a plurality of first conductive bumps disposed in the plurality of first solder resist opening patterns and a plurality of second conductive bumps disposed in the plurality of second solder resist opening patterns and disposed on the plurality of substrate pads and the plurality of device pads.
2 . The semiconductor package as claimed in claim 1 , wherein each of the plurality of first conductive bumps comprises a lower surface contacting respective one of the plurality of substrate pads and an upper surface contacting the respective one of the plurality of device pads, and a diameter of the lower surface is substantially greater than a diameter of the upper surface.
3 . The semiconductor package as claimed in claim 1 , wherein the plurality of first solder resist opening patterns are disposed on two opposite sides of the periphery of a device mounting region where the encapsulated semiconductor device is disposed.
4 . The semiconductor package as claimed in claim 1 , wherein one of the plurality of first solder resist opening patterns and respective one of the plurality of device pads are in ellipse shapes, and a major axis of one of the plurality of first solder resist opening patterns is substantially collinear with a major axis of the respective one of the plurality of device pads from a top view.
5 . The semiconductor package as claimed in claim 1 , wherein a first contact area of one of the plurality of first conductive bumps for contacting respective one of the plurality of substrate pads is substantially greater than a second contact area of the one of the plurality of first conductive bumps for contacting respective one of the plurality of device pads.
6 . The semiconductor package as claimed in claim 1 , wherein the encapsulated semiconductor device further comprises a semiconductor device encapsulated by an encapsulating material and an interposer where the semiconductor device and the encapsulating material mounted thereon, and the interposer disposed over the package substrate.
7 . The semiconductor package as claimed in claim 1 , wherein a diameter of one of the plurality of first solder resist opening patterns is substantially up to 1.5 times greater than a diameter of one of the plurality of second solder resist opening patterns.
8 . The semiconductor package as claimed in claim 1 , wherein the solder resist layer further comprises a plurality of third solder resist opening patterns fully on entire inner columns of the device mounting region adjacent to the outermost column of the plurality of first solder resist opening patterns, a diameter of each of the plurality of first solder resist opening patterns is substantially greater than a diameter of each of the plurality of third solder resist opening patterns.
9 . The semiconductor package as claimed in claim 8 , wherein the plurality of second solder resist opening patterns are surrounded by the plurality of third solder resist opening patterns, and a diameter of each of the plurality of third solder resist opening patterns is greater than a diameter of each of the plurality of second solder resist opening patterns.
10 . The semiconductor package as claimed in claim 1 , wherein a gap exists between each of the plurality of first conductive bumps and the respectively one of the plurality of first solder resist opening patterns.
11 . The semiconductor package as claimed in claim 10 , further comprising an underfill material filling a space between the package substrate and the encapsulated semiconductor device and fill the gap between each of the plurality of first conductive bumps and the respectively one of the plurality of first solder resist opening patterns.
12 . A semiconductor package, comprising:
a package substrate comprising a plurality of substrate pads, and a solder resist layer comprising a plurality of first solder resist opening patterns and a plurality of second solder resist opening patterns surrounded by the plurality of first solder resist opening patterns, wherein diameters of the plurality of substrate pads disposed on an outermost surface of the package substrate are same, and a diameter of each of the plurality of first solder resist opening patterns is substantially greater than a diameter of each of the plurality of second solder resist opening patterns;
an interposer disposed over the package substrate and comprising a plurality of device pads disposed on an outermost surface of the interposer;
a plurality of first semiconductor devices and a second semiconductor device disposed over the interposer through a plurality of connectors, wherein the plurality of first semiconductor devices are disposed along a side of the second semiconductor device, and the plurality of first solder resist opening patterns disposed along an outermost side of each of the plurality of first semiconductor devices from a top view; and
a plurality of first conductive bumps disposed in the plurality of first solder resist opening patterns respectively and a plurality of second conductive bumps disposed in the plurality of second solder resist opening patterns respectively and disposed on the plurality of device pads of the interposer and the plurality of substrate pads of the package substrate respectively.
13 . The semiconductor package as claimed in claim 12 , wherein the diameter of the each of the plurality first solder resist opening patterns is substantially greater than a diameter of each of the plurality of device pads.
14 . The semiconductor package as claimed in claim 12 , wherein the plurality of first semiconductor devices are disposed along two opposite sides of the second semiconductor device.
15 . The semiconductor package as claimed in claim 14 , wherein the plurality of first solder resist opening patterns are overlapped with a peripheral portion of the plurality of first semiconductor devices from a top view, and the plurality of conductive bumps comprises a plurality of first conductive bumps disposed in the plurality of first solder resist opening patterns and a plurality of second conductive bumps disposed in the plurality of second solder resist opening patterns, and each of the plurality of first conductive bump is spaced apart from a sidewall of respective one of the plurality of first solder resist opening patterns.
16 . The semiconductor package as claimed in claim 14 , wherein the plurality of second solder resist opening patterns are overlapped with the second semiconductor device and a portion of the plurality of first semiconductor devices from a top view.
17 . The semiconductor package as claimed in claim 12 , wherein a diameter of one of the plurality first solder resist opening patterns is substantially up to 1.5 times greater than a diameter of one of the plurality second solder resist opening patterns.
18 . The semiconductor package as claimed in claim 12 , further comprising an encapsulating material over the interposer and at least laterally encapsulating the plurality of semiconductor devices.
19 . The semiconductor package as claimed in claim 12 , wherein the plurality of first solder resist opening patterns comprises an outermost column of the plurality of first solder resist opening patterns and an inner column of the plurality of first solder resist opening patterns adjacent to the outermost column of the plurality of first solder resist opening patterns, a diameter of each of the outermost column of the plurality of first solder resist opening patterns is substantially greater than a diameter of each of the inner column of the plurality of first solder resist opening patterns.
20 . A semiconductor package, comprising:
a package substrate comprising, a plurality of substrate pads, and a solder resist layer comprising an array of a plurality of second solder resist opening patterns and a plurality of first solder resist opening patterns disposed along two opposite sides of the array of the plurality of second solder resist opening patterns wherein sizes of the plurality of substrate pads disposed on an outermost surface of the package substrate are same;
an encapsulated semiconductor device over the package substrate and comprising a plurality of semiconductor devices encapsulated by an encapsulating material and a plurality of device pads disposed on an outermost surface of the encapsulated semiconductor device, wherein a peripheral portion of the encapsulated semiconductor device is closer to the package substrate than a center portion of the encapsulated semiconductor device is, wherein one of the plurality of first solder resist opening patterns and a respective one of the plurality of device pads are in ellipse shapes, and a major axis of the one of the plurality of first solder resist opening patterns is substantially collinear with a major axis of the respective one of the plurality of device pads from a top view, and a minor axis of the respective one of the plurality of device pads is shorter than the major axis; and
a plurality of first conductive bumps disposed in the plurality of first solder resist opening patterns and a plurality of second conductive bumps disposed in the plurality of second solder resist opening patterns respectively and bonding the plurality of substrate pads and the plurality of device pads.
21 . The semiconductor package as claimed in claim 20 , wherein the encapsulated semiconductor device further comprises an interposer comprising the plurality of device pads and disposed over the device mounting region, a semiconductor device disposed over the interposer and encapsulated by an encapsulating material.
22 . The semiconductor package as claimed in claim 20 , wherein one of the plurality of first solder resist opening patterns and respective one of the plurality of device pads are in ellipse shapes, from a top view, and a long axis of the one of the plurality of first solder resist opening patterns is substantially longer than a short axis of the one of the plurality first solder resist opening patterns.
23 . The semiconductor package as claimed in claim 22 , wherein a size of each of the plurality of first solder resist opening pattern is substantially greater than a size of each of the plurality of second solder resist opening patterns.