Semiconductor structure and method for forming the same

1 . A method for forming a semiconductor structure comprising:

forming a plurality of field-effect transistor (FET) devices over a semiconductor substrate, wherein each of the FET devices comprises a sacrificial gate structure;

forming an etch stop layer over the substrate and the FET devices, wherein the etch stop layer covers top surfaces of the sacrificial gate structures;

forming an inter-layer (ILD) structure over the etch stop layer and the substrate and surrounding the FET devices, and covering the top surfaces of the sacrificial gate structures;

forming a protecting structure in the ILD structure after the forming of the ILD structure;

removing portions of the ILD structure and portions of the etch stop layer to expose the top surfaces of the sacrificial gate structures, wherein a top surface of the etch stop layer, a top surface of the ILD structure, a top surface of the protecting structure and the top surfaces of the sacrificial gate structures are aligned with each other;

removing the sacrificial gate structures to form gate trenches after the forming of the protecting structure and the removing of the portion of the ILD structure; and

forming a metal gate structure in each of the gate trenches;

wherein the removing of the portions of the ILD structure and the portions of the etch stop layer comprises:

performing a chemical-mechanical polishing (CMP) operation,

wherein a removing rate of the protecting structure is lower than a removing rate of the ILD structure in the CMP operation.

2 . The method of claim 1 , wherein the gate trenches are offset from the protecting structure.

3 . The method of claim 1 , wherein the forming of the metal gate structure further comprising:

forming a work function metal layer in the gate trenches;

filling the gate trenches with a gap-filling metal layer; and

removing superfluous gap-filling metal layer and work function metal layer.

4 . A method for forming a semiconductor structure comprising: forming a plurality of FET devices over a semiconductor substrate, wherein each of the FET devices comprises a sacrificial gate structure and a source/drain;

forming an etch stop layer over the substrate and the FET devices, wherein the etch stop layer covers top surfaces of the sacrificial gate structures and top surfaces of the sources/drains;

forming an ILD structure over the etch stop layer, the substrate and the FET devices;

forming a doped region in the ILD structure between the sacrificial gate structures of adjacent two FET devices, wherein a bottom and a sidewall of the doped region are in contact with the ILD structure, and the doped region is separated from the sources/drains of the FET devices by the ILD structure and the etch stop layer;

removing portions of the ILD structure and portions of the etch stop layer;

exposing the top surfaces of the sacrificial gate structures, wherein a top surface of the etch stop layer, a top surface of the ILD structure, a top surface of the doped region and the top surfaces of the sacrificial gate structures are aligned with each other; and

replacing the sacrificial gate structures with metal gate structures;

wherein the removing of the portions of the ILD structure and the portions of the etch stop layer comprises a CMP operation, and

a removing rate of the doped region is lower than a removing rate of the ILD structure in the CMP operation.

5 . The method of claim 4 , wherein the forming of the doped region comprises:

forming a patterned mask over the ILD structure, wherein the patterned mask comprises an opening exposing a portion of the ILD structure between the adjacent two sacrificial gate structures; and

performing an ion implantation to the portion of the ILD structure to form the doped region through the opening.

6 . The method of claim 5 , wherein a width of the patterned mask is greater than a width of each sacrificial gate structure.

7 . The method of claim 5 , wherein the patterned mask comprises a patterned photoresist.

8 . The method of claim 5 , wherein the ion implantation comprises nitrogen.

9 . The method of claim 8 , wherein a concentration of the nitrogen in the doped region is between approximately 1.0E14 atom/cm 3 and approximately 1.0E16 atom/cm 3 .

10 . The method of claim 4 , wherein a depth of the doped region is less than a thickness of the ILD structure.

11 . The method of claim 10 , wherein the depth of the doped region is greater than a half of heights of the sacrificial gate structures.

12 . The method of claim 4 , wherein the ILD structure is conformally formed over the substrate and the FET devices.

13 . The method of claim 12 , wherein the ILD structure comprises first portions over the sacrificial gate structures and second portions between the first portions, and top surfaces are at a level different from that of top surfaces of the second portions.

14 . The method of claim 4 , wherein the doped region comprises a dielectric material same as that of the ILD structure.

15 . A method for forming a semiconductor structure comprising:

forming a FET device over a semiconductor substrate, wherein the FET device comprises a sacrificial gate structure and a source/drain;

forming an etch stop layer over a top surface of the sacrificial gate structure and a top surface of the source/drain;

forming an ILD structure over the etch stop layer, the substrate and the FET device;

forming a patterned mask over the ILD structure, wherein the patterned mask overlaps the sacrificial gate structure;

performing an ion implantation to form an nitrogen (N)-doped region in the ILD structure after the forming of the patterned mask, wherein the N-doped region is offset from the sacrificial gate structure and the N-doped region is separated from the source/drain of the FET device by the ILD structure;

removing a portion of the ILD structure, a portion of the etch stop layer and a portion of the N-doped region;

exposing the top surface of the sacrificial gate structure, wherein a top surface of the etch stop layer, a top surface of the ILD structure, a top surface of the N-doped region and the top surface of the sacrificial gate structure are aligned with each other;

removing the sacrificial gate structure to form a gate trench; and

forming a metal gate structure in the gate trench;

wherein a concentration of the nitrogen in the N-doped region is between approximately 1.0E14 atom/cm3 and approximately 1.0E16 atom/cm3;

further comprises a spacer disposed between the metal gate structure and the ILD structure, wherein sidewalls of the N-doped region are separated from the spacer by the ILD structure;

wherein the N-doped region is separated from the CESL by the ILD structure wherein the N-doped region comprises a dielectric material same as that of the ILD structure.