Integrated circuit structure and manufacturing method thereof
An integrated circuit structure includes a semiconductor substrate, a passivation layer, a first protective layer, and a second protective layer. The passivation layer is over the semiconductor substrate. The first protective layer is over the passivation layer. The second protective layer is over the first protective layer, wherein a boundary of the first protective layer is confined within the second protective layer.
1 . An integrated circuit structure, comprising:
a semiconductor substrate;
a passivation layer over the semiconductor substrate;
a first protective layer over the passivation layer;
a second protective layer over the first protective layer, wherein a boundary of the first protective layer is confined within the second protective layer; and
a seal ring over a periphery of the semiconductor substrate, wherein the passivation layer covers the seal ring and comprises a protruded portion conforming to a contour of the seal ring, and the first protective layer is spaced apart from the protruded portion.
2 . The integrated circuit structure as claimed in claim 1 , wherein a material of the second protective layer is the same as a material of the first protective layer.
3 . The integrated circuit structure as claimed in claim 1 , wherein the second protective layer is interposed between the first protective layer and the protruded portion.
4 . The integrated circuit structure as claimed in claim 1 , further comprising:
a third protective layer disposed between the first protective layer and the second protective layer, wherein the second protective layer is in contact with an outer edge of the third protective layer and covers an interface between the first protective layer and the third protective layer.
5 . An integrated circuit structure, comprising:
a semiconductor substrate;
a passivation layer over the semiconductor substrate;
a first protective layer over the passivation layer;
a second protective layer over the first protective layer, wherein a boundary of the first protective layer is confined within the second protective layer; and
a seal ring over a periphery of the semiconductor substrate, wherein the passivation layer covers the seal ring.
6 . The integrated circuit structure as claimed in claim 5 , wherein the second protective layer is in contact with an outer edge of the first protective layer and covers an interface between the first protective layer and the passivation layer.
7 . The integrated circuit structure as claimed in claim 5 , wherein the first protective layer is completely overlapped with the second protective layer from a top view.
8 . The integrated circuit structure as claimed in claim 5 , further comprising:
a third protective layer disposed between the first protective layer and the second protective layer, wherein the second protective layer is in contact with an outer edge of the third protective layer and covers an interface between the first protective layer and the third protective layer.
9 . The integrated circuit structure as claimed in claim 5 , further comprising:
a plurality of conductive bumps over and partially embedded in the second protective layer.
10 . The integrated circuit structure as claimed in claim 5 ,
wherein the second protective layer is overlapped with the seal ring from a top view.
11 . The integrated circuit structure as claimed in claim 10 , wherein the passivation layer is disposed over the seal ring and comprises a protruded portion covering and conforming to a contour of the seal ring, and the first protective layer is spaced apart from the protruded portion.
12 . The integrated circuit structure as claimed in claim 11 , wherein the second protective layer covers a part of the protruded portion and the passivation layer between the first protective layer and the protruded portion.
13 . An integrated circuit structure, comprising:
a semiconductor substrate;
a conductive layer over the semiconductor substrate, wherein the conductive layer comprises a seal ring over a periphery of the semiconductor substrate;
a passivation layer covering the seal ring in a conformal manner;
a first protective layer over the passivation layer; and
a second protective layer covering the first protective layer and an interface between the first protective layer and the passivation layer.
14 . The integrated circuit structure as claimed in claim 13 , wherein an outer edge of the second protective layer is a planar surface extended from an upper surface of the second protective layer to the passivation layer.
15 . The integrated circuit structure as claimed in claim 13 , further comprising:
a plurality of conductive bumps over and partially embedded in the second protective layer, wherein the plurality of conductive bumps are electrically connected to the conductive layer.
16 . The integrated circuit structure as claimed in claim 13 , further comprising:
a third protective layer disposed between the first protective layer and the second protective layer, wherein the second protective layer at least covers an outer edge of the third protective layer and an interface between the first protective layer and the third protective layer.
17 . The integrated circuit structure as claimed in claim 16 , wherein the third protective layer reveals a periphery of the first protective layer, which is covered by the second protective layer.
18 . The integrated circuit structure as claimed in claim 13 , wherein the second protective layer is overlapped with the seal ring from a top view.
19 . The integrated circuit structure as claimed in claim 18 , wherein the passivation layer is disposed over the seal ring and comprises a protruded portion covering and conforming to a contour of the seal ring, and the first protective layer is spaced apart from the protruded portion.
20 . The integrated circuit structure as claimed in claim 19 , wherein the second protective layer covers a space between the first protective layer and the protruded portion and a part of the protruded portion.