IP Library Granted Patent US 12696800
Granted Patent B2
US 12696800 · App. 17/848,246 · Granted Jul 28, 2026

Microelectronic assemblies including solder and non-solder interconnects

Inventors: Alois Nitsch (Munich, DE); Han-Wen Lin (Zhubei City, TW); Yin-Ying Chen (Hsinchu City, TW); Meng-Chi Lee (Taipei, TW); Andreas Dost (Freising, DE); Hans Gerard Jetten (Anzing, DE)
Assignee: Intel Corporation
H10W90/00H10P72/74H10W70/05H10W70/09H10W70/093H10W70/611H10W70/65H10W70/685H10W74/016H10W74/019H10P72/7436H10W70/6528H10W90/20H10W90/291
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Quick Facts
Patent No.
US 12696800
App. No.
17/848,246
Granted
Jul 28, 2026
Kind
B2
Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface; a redistribution layer (RDL) having a surface, wherein the first surface of the first die is on and electrically coupled to the surface of the RDL by non-solder interconnects; and a second die at the second surface of the first die, wherein the second die is electrically coupled directly to the second surface of the first die by solder interconnects.

Claims (40)

1 . A microelectronic assembly, comprising:

a package substrate;

a first die, having a first surface and an opposing second surface;

a redistribution layer (RDL) having a first surface and an opposing second surface, wherein the first surface of the first die is on and coupled to the second surface of the RDL by first non-solder interconnects and the first surface of the RDL is on and coupled to a surface of the package substrate by first solder interconnects;

a second die at the second surface of the first die, wherein the second die is coupled directly to the second surface of the first die by second solder interconnects;

an insulating material extending from the second surface of the RDL, around the first die, around the second solder interconnects, and at least partially around the second die, wherein the insulating material is continuous; and

a conductive pillar having a first end and a second end opposite the first end, wherein the first end of the conductive pillar is coupled to the second surface of the RDL by second non-solder interconnects and the second end of the conductive pillar is coupled to the second die by third non-solder interconnects, and wherein the conductive pillar is through the insulating material.

2 . The microelectronic assembly of claim 1 , wherein the non-solder interconnects include metal-to-metal interconnects.

3 . The microelectronic assembly of claim 1 , wherein a pitch of the non-solder interconnects is between 10 microns and 150 microns.

4 . The microelectronic assembly of claim 1 , wherein a pitch of the second solder interconnects is between 10 microns and 50 microns.

5 . The microelectronic assembly of claim 1 , wherein the insulating material includes an organic polymer with inorganic particles, a resin material, or an epoxy material.

6 . The microelectronic assembly of claim 1 , wherein the first die is coupled to the package substrate by the first non-solder interconnects, conductive pathways in the RDL, and the first solder interconnects.

7 . The microelectronic assembly of claim 1 , wherein the second die is coupled to the package substrate by the third non-solder interconnects, the conductive pillar, the second non-solder interconnects, conductive pathways in the RDL, and the first solder interconnects.

8 . A microelectronic assembly, comprising:

a package substrate;

a redistribution layer (RDL) having a first surface and an opposing second surface, wherein the first surface of the RDL is on and coupled to a surface of the package substrate by first solder interconnects;

a first die, having a first surface and an opposing second surface, wherein the first surface of the first die is coupled to the second surface of the RDL by first non-solder interconnects;

a second die at the second surface of the first die, wherein the second die is coupled directly to the second surface of the first die by second solder interconnects;

a third die at the second surface of the first die, wherein the third die is coupled directly to the second surface of the first die by third solder interconnects;

a single layer of an insulating material on the second surface of the RDL, around the first die, around the second solder interconnects and the third solder interconnects, and at least partially around the second and third dies;

a first conductive pillar having a first end and a second end opposite the first end, wherein the first end of the first conductive pillar is coupled to the second surface of the RDL by second non-solder interconnects and the second end of the first conductive pillar is coupled to the second die by third non-solder interconnects, and wherein the first conductive pillar is through the single layer of an insulating material; and

a second conductive pillar having a first end and a second end opposite the first end, wherein the first end of the second conductive pillar is coupled to the second surface of the RDL by fourth non-solder interconnects and the second end of the second conductive pillar is coupled to the third die by fifth non-solder interconnects, and wherein the second conductive pillar is through the single layer of an insulating material.

9 . The microelectronic assembly of claim 8 , wherein the insulating material includes an organic polymer with inorganic particles, a resin material, or an epoxy material.

10 . The microelectronic assembly of claim 8 , wherein the surface of the package substrate is a second surface and the package substrate further includes a first surface opposite the second surface, and the microelectronic assembly further comprising:

a circuit board coupled to the first surface of the package substrate by third solder interconnects.

11 . A microelectronic assembly, comprising:

a package substrate;

a redistribution layer (RDL), having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, wherein the first conductive contacts on the RDL are coupled to a surface of the package substrate by first solder interconnects;

a first die layer including a first die, having a first surface with third conductive contacts and an opposing second surface with fourth conductive contacts, wherein the third conductive contacts on the first die are coupled to the second conductive contacts on the RDL by first non-solder interconnects;

a second die layer, on the first die layer, including a second die and a third die, wherein:

the second die has a surface with fifth conductive contacts coupled to the fourth conductive contacts on the first die by solder interconnects, and

the third die has a surface with sixth conductive contacts;

an insulating material extending from the second surface of the RDL, around the first die, around the second solder interconnects, and at least partially around the second die and the third die, wherein the insulating material is continuous; and

a conductive pillar, through the insulating material, having a first end and a second end opposite the first end, wherein the first end of the conductive pillar is coupled to the second surface of the RDL by second non-solder interconnects and the second end of the conductive pillar is coupled to the sixth conductive contacts on the third die by third non-solder interconnects.

12 . The microelectronic assembly of claim 11 , wherein the insulating material includes an organic polymer with inorganic particles, a resin material, or an epoxy material.

13 . The microelectronic assembly of claim 11 , wherein a pitch of the second solder interconnects is between 10 microns and 50 microns.

14 . The microelectronic assembly of claim 11 , wherein a pitch of the first non-solder interconnects is between 10 microns and 150 microns.

15 . The microelectronic assembly of claim 11 , wherein the fifth conductive contacts are recessed or flush with the surface of the second die.

16 . The microelectronic assembly of claim 11 , wherein the fifth conductive contacts extend away from the surface of the second die.

17 . The microelectronic assembly of claim 11 , wherein the first non-solder interconnects include metal-to-metal interconnects.