Package architecture with compute bricks having vertically stacked dies
Embodiments of a microelectronic assembly comprise: a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die, and a second plurality of IC dies coupled to at least the first IC die or the second IC die. Each IC die in the first plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective first planar interface, each of the first IC die and the second IC die includes a respective substrate and a respective metallization stack attached along a respective second planar interface, each IC die in the second plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective third planar interface, and the first planar interface is orthogonal to the second planar interface.
1 . A microelectronic assembly, comprising:
a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and
a second plurality of IC dies coupled to at least the first IC die or the second IC die,
wherein:
each IC die in the first plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective first planar interface,
each of the first IC die and the second IC die includes a respective substrate and a respective metallization stack attached along a respective second planar interface,
each IC die in the second plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective third planar interface, and
the first planar interface is orthogonal to the second planar interface.
2 . The microelectronic assembly of claim 1 , wherein the second planar interface is parallel to the third planar interface.
3 . The microelectronic assembly of claim 1 , wherein:
the first IC die and the second IC die comprise through-substrate vias (TSVs),
each of the first IC die and the second IC die have a respective first surface and a respective second surface opposite to the first surface, and
the respective first surfaces are coupled to opposite sides of IC dies in the first plurality of IC dies.
4 . The microelectronic assembly of claim 3 , wherein:
a first subset of the second plurality of IC dies is coupled to the second surface of the first IC die, and
a second subset of the second plurality of IC dies is coupled to the second surface of the second IC die.
5 . The microelectronic assembly of claim 1 , wherein:
at least one of the IC die in the first plurality of IC dies comprises two metallization stacks attached on either side of the respective substrate along first planar interfaces, with one of the two metallization stacks comprising optical structures, and
other IC dies in the first plurality of IC dies comprise two metallization stacks attached on either side of the respective substrates along first planar interfaces, with conductive traces in one of the two metallization stacks being thicker than conductive traces in the other of the two metallization stacks.
6 . The microelectronic assembly of claim 1 , wherein the first IC die and the second IC die are coupled to the first plurality of IC dies by metal-metal bonds and dielectric-dielectric bonds.
7 . The microelectronic assembly of claim 1 , wherein the second plurality of IC dies is coupled to the first IC die or the second IC die by metal-metal bonds and dielectric-dielectric bonds.
8 . The microelectronic assembly of claim 1 , wherein IC dies in the first plurality of IC dies are mutually parallel and spaced apart from each other by a gap.
9 . The microelectronic assembly of claim 1 , further comprising at least one support structure parallel to the first plurality of IC dies, wherein the support structure is mechanically coupled to the first IC die and the second IC die.
10 . The microelectronic assembly of claim 1 , wherein:
at least some IC dies in the first plurality of IC dies comprises compute circuitry,
at least one of the first IC die or the second IC die comprises network circuitry, and
at least some IC dies in the second plurality of IC dies comprises memory circuitry.
11 . A microelectronic assembly, comprising:
a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and
a second plurality of IC dies coupled to at least the first IC die or the second IC die,
wherein:
each IC die in the first plurality of IC dies includes a respective substrate and two metallization stacks attached on either side of the respective substrate along first planar interfaces,
at least one of the IC die in the first plurality of IC dies comprises two metallization stacks attached on either side of the respective substrate along first planar interfaces,
each of the first IC die and the second IC die includes a respective substrate and a respective metallization stack attached along a respective second planar interface,
each IC die in the second plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective third planar interface, and
the first planar interface is orthogonal to the second planar interface.
12 . The microelectronic assembly of claim 11 , wherein the second planar interface is parallel to the third planar interface.
13 . The microelectronic assembly of claim 11 , wherein:
the first IC die and the second IC die comprise through-substrate vias (TSVs),
each of the first IC die and the second IC die have a respective first surface and a respective second surface opposite to the first surface, and
the respective first surfaces are coupled to opposite sides of IC dies in the first plurality of IC dies.
14 . The microelectronic assembly of claim 13 , wherein:
a first subset of the second plurality of IC dies is coupled to the second surface of the first IC die, and
a second subset of the second plurality of IC dies is coupled to the second surface of the second IC die.
15 . The microelectronic assembly of claim 11 , wherein the at least one of the IC die in the first plurality of IC dies comprising two metallization stacks includes one of the metallization stacks having optical structures, and the microelectronic assembly further comprising:
an other IC die in the first plurality of IC dies comprising two metallization stacks attached on either side of the respective substrate along first planar interfaces, and one of the two metallization stacks has conductive traces that are thicker than conductive traces in the other of the two metallization stacks.
16 . The microelectronic assembly of claim 11 , wherein:
at least some IC dies in the first plurality of IC dies comprises compute circuitry,
at least one of the first IC die or the second IC die comprises network circuitry, and
at least some IC dies in the second plurality of IC dies comprises memory circuitry.