Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
1 . A semiconductor device assembly, comprising:
a support substrate, a top surface of the support substrate having one or more first bond pads;
a first semiconductor die carried by the support substrate;
a second semiconductor die carried by the first semiconductor die, the second semiconductor die having an upper surface and a redistribution network having a second bond pad at the upper surface, wherein the upper surface has a longitudinal footprint;
an encapsulant encasing the first semiconductor die and the second semiconductor die;
a wirebond electrically coupled between a first bond pad of the one or more first bond pads on the support substrate and a third bond pad at a top surface of the first semiconductor die, wherein a portion of the wirebond is encased in a material, different from the encapsulant, between the top surface of the first semiconductor die and a bottom surface of the second semiconductor die; and
a cylindrical interconnect attached to the second bond pad at the upper surface of the second semiconductor die, wherein at least a portion of the cylindrical interconnect extends beyond an outer surface of the encapsulant within the longitudinal footprint of the upper surface, and wherein the cylindrical interconnect has a cylindrical shape with a planar upper surface.
2 . The semiconductor device assembly of claim 1 wherein the second semiconductor die further includes a lower surface and a through substrate via electrically connecting the upper surface to the lower surface.
3 . The semiconductor device assembly of claim 2 wherein the through substrate via is electrically coupled to the first semiconductor die at the lower surface of the second semiconductor die.
4 . The semiconductor device assembly of claim 2 wherein the first semiconductor die comprises the top surface, a bottom surface, and a second through substrate via electrically connecting the top surface to the bottom surface.
5 . The semiconductor device assembly of claim 1 wherein the semiconductor device assembly further comprises a second wirebond electrically coupled between a second surface bond pad on the support substrate and a fourth bond pad coupled with the upper surface of the redistribution network.
6 . The semiconductor device assembly of claim 5 wherein the second bond pad is electrically coupled to the fourth bond pad through a conductive trace in the redistribution network.
7 . A semiconductor device assembly, comprising:
a support substrate comprising one or more first bond pads;
a first semiconductor device carried by the support substrate, the first semiconductor device comprising:
a second bond pad at a top surface of the first semiconductor device; and
a wirebond;
a second semiconductor device carried by the first semiconductor device, the second semiconductor device comprising:
an upper surface and a lower surface, wherein the wirebond is electrically coupled between a first bond pad of the one or more first bond pads and the second bond pad, wherein a portion of the wirebond is encased in a material between the top surface of the first semiconductor device and the lower surface of the second semiconductor device;
an array of third bond pads at the upper surface; and
a redistribution network at the upper surface, the redistribution network having an array of fourth bond pads;
an encapsulant encasing the first semiconductor device and the second semiconductor device, wherein the material is different from the encapsulant; and
an array of cylindrical interconnects each attached to a corresponding fourth bond pad in the array of fourth bond pads, wherein at least a portion of each cylindrical interconnect in the array of interconnects extends beyond an outer surface of the encapsulant, and wherein each cylindrical interconnect of the array of cylindrical interconnects has a cylindrical shape with a planar upper surface.
8 . The semiconductor device assembly of claim 7 wherein the upper surface includes central portion having a passivation material, wherein the redistribution network is formed in the passivation material and the array of fourth bond pads is carried by the passivation material, and wherein the array of third bond pads is carried by a peripheral portion of the upper surface.
9 . The semiconductor device assembly of claim 7 wherein a top surface of each of the third bond pads is at a first elevation, and wherein a top surface of each of the fourth bond pads is at a second elevation higher than the first elevation.
10 . The semiconductor device assembly of claim 7 wherein the array of third bond pads has a first pitch, and wherein the array of fourth bond pads has a second pitch smaller than the first pitch.
11 . The semiconductor device assembly of claim 7 wherein each third bond pad in the array of third bond pads has a first surface area, and wherein each fourth bond pad in the array of fourth bond pads has a second surface area smaller than the first surface area.
12 . The semiconductor device assembly of claim 7 , wherein each individual third bond pad in the array of third bond pads is electrically coupled to a corresponding substrate bond pad on the support substrate through a second wirebond.
13 . The semiconductor device assembly of claim 7 wherein the array of fourth bond pads is electrically coupled to the array of third bond pads through one or more traces in the redistribution network.
14 . The semiconductor device assembly of claim 7 wherein the second semiconductor device further comprises internal circuitry, and wherein one or more third bond pads in the array of third bond pads is electrically coupled to the internal circuitry.
15 . A stacked semiconductor package assembly, comprising:
a first semiconductor package, the first semiconductor package comprising:
a first support substrate having a first surface and a second surface opposite the first surface, wherein the first surface includes one or more substrate bond pads, and wherein the second surface includes one or more exterior bond pads;
a first semiconductor die carried by the first surface of the first support substrate, the first semiconductor die having an active surface and one or more first bond pads at the active surface;
a second semiconductor die carried by the first semiconductor die;
one or more wirebonds extending between individual pairs of the one or more first bond pads and the one or more substrate bond pads; and
a first encapsulant encasing the first semiconductor die and the one or more wirebonds, wherein respective portions of the one or more wirebonds are encased in a material, different from the first encapsulant, between the active surface of the first semiconductor die and a bottom surface of the second semiconductor die; and
a second semiconductor package, the second semiconductor package comprising:
a second support substrate;
a third semiconductor die carried by the second support substrate, the third semiconductor die having an active surface and a redistribution network at the active surface, wherein the redistribution network includes one or more second bond pads;
a second encapsulant encasing the third semiconductor die; and
one or more cylindrical interconnects individually attached to each of the one or more second bond pads, wherein at least a portion of each cylindrical interconnect of the one or more cylindrical interconnects extends beyond an outer surface of the second encapsulant and is electrically coupled to the one or more exterior bond pads on the second surface of the first support substrate, and wherein each cylindrical interconnect of the one or more cylindrical interconnects has a cylindrical shape with a planar upper surface.
16 . The stacked semiconductor package assembly of claim 15 , further comprising one or more solder balls electrically coupling corresponding pairs of the one or more cylindrical interconnects and the one or more exterior bond pads on the second surface of the first support substrate.
17 . The stacked semiconductor package assembly of claim 15 wherein each cylindrical interconnect of the one or more cylindrical interconnects is vertically aligned with the active surface of the second semiconductor die.